riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #include <cstdint>
  11 #include <string.h>
  12 #include <strings.h>
  13 #include "encoding.h"
  14 #include "config.h"
  15 #include "common.h"
  16 #include <cinttypes>
  17
  18 typedef int64_t sreg_t;
  19 typedef uint64_t reg_t;
  20 typedef uint64_t freg_t;
  21
  22 const int NXPR = 32;
  23 const int NFPR = 32;
  24
  25 #define FP_RD_NE  0
  26 #define FP_RD_0   1
  27 #define FP_RD_DN  2
  28 #define FP_RD_UP  3
  29 #define FP_RD_NMM 4
  30
  31 #define FSR_RD_SHIFT 5
  32 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  33
  34 #define FPEXC_NX 0x01
  35 #define FPEXC_UF 0x02
  36 #define FPEXC_OF 0x04
  37 #define FPEXC_DZ 0x08
  38 #define FPEXC_NV 0x10
  39
  40 #define FSR_AEXC_SHIFT 0
  41 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  42 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  43 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  44 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  45 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  46 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  47
  48 #define insn_length(x) \
  49   (((x) & 0x03) < 0x03 ? 2 : \
  50    ((x) & 0x1f) < 0x1f ? 4 : \
  51    ((x) & 0x3f) < 0x3f ? 6 : \
  52    8)
  53
  54 typedef uint64_t insn_bits_t;
  55 class insn_t
  56 {
  57 public:
  58   insn_t() = default;
  59   insn_t(insn_bits_t bits) : b(bits) {}
  60   insn_bits_t bits() { return b; }
  61   int length() { return insn_length(b); }
  62   int64_t i_imm() { return int64_t(b) >> 20; }
  63   int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
  64   int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
  65   int64_t u_imm() { return int64_t(b) >> 12 << 12; }
  66   int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
  67   uint64_t rd() { return x(7, 5); }
  68   uint64_t rs1() { return x(15, 5); }
  69   uint64_t rs2() { return x(20, 5); }
  70   uint64_t rs3() { return x(27, 5); }
  71   uint64_t rm() { return x(12, 3); }
  72   uint64_t csr() { return x(20, 12); }
  73
  74   int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); }
  75   int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); }
  76   int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); }
  77   int64_t rvc_lw_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); }
  78   int64_t rvc_ld_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 7) + (x(12, 1) << 5); }
  79   int64_t rvc_j_imm() { return (xs(2, 3) << 9) + (x(5, 2) << 3) + (x(7, 1) << 1) + (x(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); }
  80   int64_t rvc_b_imm() { return (x(5, 2) << 3) + (x(7, 1) << 1) + (xs(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); }
  81   uint64_t rvc_rd() { return rd(); }
  82   uint64_t rvc_rs1() { return x(2, 5); }
  83   uint64_t rvc_rs2() { return rd(); }
  84   uint64_t rvc_rds() { return 8 + x(7, 3); }
  85   uint64_t rvc_rs1s() { return 8 + x(2, 3); }
  86   uint64_t rvc_rs2s() { return rvc_rds(); }
  87 private:
  88   insn_bits_t b;
  89   uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
  90   uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
  91   uint64_t imm_sign() { return xs(63, 1); }
  92 };
  93
  94 template <class T, size_t N, bool zero_reg>
  95 class regfile_t
  96 {
  97 public:
  98   void write(size_t i, T value)
  99   {
 100     if (!zero_reg || i != 0)
 101       data[i] = value;
 102   }
 103   const T& operator [] (size_t i) const
 104   {
 105     return data[i];
 106   }
 107 private:
 108   T data[N];
 109 };
 110
 111 // helpful macros, etc
 112 #define MMU (*p->get_mmu())
 113 #define STATE (*p->get_state())
 114 #define RS1 STATE.XPR[insn.rs1()]
 115 #define RS2 STATE.XPR[insn.rs2()]
 116 #define WRITE_REG(reg, value) STATE.XPR.write(reg, value)
 117 #define WRITE_RD(value) WRITE_REG(insn.rd(), value)
 118
 119 #ifdef RISCV_ENABLE_COMMITLOG
 120   #undef WRITE_REG
 121   #define WRITE_REG(reg, value) ({ \
 122         reg_t wdata = value; /* value is a func with side-effects */ \
 123         STATE.log_reg_write = (commit_log_reg_t){reg << 1, wdata}; \
 124         STATE.XPR.write(reg, wdata); \
 125       })
 126 #endif
 127
 128 // RVC macros
 129 #define WRITE_RVC_RDS(value) WRITE_REG(insn.rvc_rds(), value)
 130 #define RVC_RS1 STATE.XPR[insn.rvc_rs1()]
 131 #define RVC_RS2 STATE.XPR[insn.rvc_rs2()]
 132 #define RVC_RS1S STATE.XPR[insn.rvc_rs1s()]
 133 #define RVC_RS2S STATE.XPR[insn.rvc_rs2s()]
 134 #define RVC_SP STATE.XPR[2]
 135
 136 // FPU macros
 137 #define FRS1 STATE.FPR[insn.rs1()]
 138 #define FRS2 STATE.FPR[insn.rs2()]
 139 #define FRS3 STATE.FPR[insn.rs3()]
 140 #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
 141 #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD))
 142 #define do_write_frd(value) (STATE.FPR.write(insn.rd(), value), dirty_fp_state)
 143
 144 #ifndef RISCV_ENABLE_COMMITLOG
 145 # define WRITE_FRD(value) do_write_frd(value)
 146 #else
 147 # define WRITE_FRD(value) ({ \
 148         freg_t wdata = (value); /* value may have side effects */ \
 149         STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
 150         do_write_frd(wdata); \
 151       })
 152 #endif
 153
 154 #define SHAMT (insn.i_imm() & 0x3F)
 155 #define BRANCH_TARGET (pc + insn.sb_imm())
 156 #define JUMP_TARGET (pc + insn.uj_imm())
 157 #define RM ({ int rm = insn.rm(); \
 158               if(rm == 7) rm = STATE.frm; \
 159               if(rm > 4) throw trap_illegal_instruction(); \
 160               rm; })
 161
 162 #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1)))
 163 #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask)))
 164
 165 #define require_privilege(p) if (get_field(STATE.mstatus, MSTATUS_PRV) < (p)) throw trap_illegal_instruction()
 166 #define require_rv64 if(unlikely(xlen != 64)) throw trap_illegal_instruction()
 167 #define require_rv32 if(unlikely(xlen != 32)) throw trap_illegal_instruction()
 168 #define require_extension(s) if (!p->supports_extension(s)) throw trap_illegal_instruction()
 169 #define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction()
 170 #define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction()
 171
 172 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
 173                              softfloat_exceptionFlags = 0; })
 174
 175 #define sext32(x) ((sreg_t)(int32_t)(x))
 176 #define zext32(x) ((reg_t)(uint32_t)(x))
 177 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
 178 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 179
 180 #define set_pc(x) \
 181   do { if (unlikely(((x) & 2)) && !p->supports_extension('C')) \
 182          throw trap_instruction_address_misaligned(x); \
 183        npc = sext_xlen(x); \
 184      } while(0)
 185
 186 #define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */
 187
 188 #define validate_csr(which, write) ({ \
 189   if (!STATE.serialized) return PC_SERIALIZE; \
 190   STATE.serialized = false; \
 191   unsigned my_priv = get_field(STATE.mstatus, MSTATUS_PRV); \
 192   unsigned csr_priv = get_field((which), 0x300); \
 193   unsigned csr_read_only = get_field((which), 0xC00) == 3; \
 194   if (((write) && csr_read_only) || my_priv < csr_priv) \
 195     throw trap_illegal_instruction(); \
 196   (which); })
 197
 198 #endif