riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6 #include "pcr.h"
   7
   8 typedef int int128_t __attribute__((mode(TI)));
   9 typedef unsigned int uint128_t __attribute__((mode(TI)));
  10
  11 typedef int64_t sreg_t;
  12 typedef uint64_t reg_t;
  13 typedef uint64_t freg_t;
  14
  15 const int OPCODE_BITS = 7;
  16
  17 const int XPRID_BITS = 5;
  18 const int NXPR = 1 << XPRID_BITS;
  19
  20 const int FPR_BITS = 64;
  21 const int FPRID_BITS = 5;
  22 const int NFPR = 1 << FPRID_BITS;
  23
  24 const int IMM_BITS = 12;
  25 const int IMMLO_BITS = 7;
  26 const int TARGET_BITS = 25;
  27 const int FUNCT_BITS = 3;
  28 const int FUNCTR_BITS = 7;
  29 const int FFUNCT_BITS = 2;
  30 const int RM_BITS = 3;
  31 const int BIGIMM_BITS = 20;
  32 const int BRANCH_ALIGN_BITS = 1;
  33 const int JUMP_ALIGN_BITS = 1;
  34
  35 #define FP_RD_NE  0
  36 #define FP_RD_0   1
  37 #define FP_RD_DN  2
  38 #define FP_RD_UP  3
  39 #define FP_RD_NMM 4
  40
  41 #define FSR_RD_SHIFT 5
  42 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  43
  44 #define FPEXC_NX 0x01
  45 #define FPEXC_UF 0x02
  46 #define FPEXC_OF 0x04
  47 #define FPEXC_DZ 0x08
  48 #define FPEXC_NV 0x10
  49
  50 #define FSR_AEXC_SHIFT 0
  51 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  52 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  53 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  54 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  55 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  56 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  57
  58 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  59
  60 // note: bit fields are in little-endian order
  61 struct itype_t
  62 {
  63   unsigned opcode : OPCODE_BITS;
  64   unsigned funct : FUNCT_BITS;
  65   signed imm12 : IMM_BITS;
  66   unsigned rs1 : XPRID_BITS;
  67   unsigned rd : XPRID_BITS;
  68 };
  69
  70 struct btype_t
  71 {
  72   unsigned opcode : OPCODE_BITS;
  73   unsigned funct : FUNCT_BITS;
  74   unsigned immlo : IMMLO_BITS;
  75   unsigned rs2 : XPRID_BITS;
  76   unsigned rs1 : XPRID_BITS;
  77   signed immhi : IMM_BITS-IMMLO_BITS;
  78 };
  79
  80 struct jtype_t
  81 {
  82   unsigned jump_opcode : OPCODE_BITS;
  83   signed target : TARGET_BITS;
  84 };
  85
  86 struct rtype_t
  87 {
  88   unsigned opcode : OPCODE_BITS;
  89   unsigned funct : FUNCT_BITS;
  90   unsigned functr : FUNCTR_BITS;
  91   unsigned rs2 : XPRID_BITS;
  92   unsigned rs1 : XPRID_BITS;
  93   unsigned rd : XPRID_BITS;
  94 };
  95
  96 struct ltype_t
  97 {
  98   unsigned opcode : OPCODE_BITS;
  99   unsigned bigimm : BIGIMM_BITS;
 100   unsigned rd : XPRID_BITS;
 101 };
 102
 103 struct ftype_t
 104 {
 105   unsigned opcode : OPCODE_BITS;
 106   unsigned ffunct : FFUNCT_BITS;
 107   unsigned rm : RM_BITS;
 108   unsigned rs3 : FPRID_BITS;
 109   unsigned rs2 : FPRID_BITS;
 110   unsigned rs1 : FPRID_BITS;
 111   unsigned rd  : FPRID_BITS;
 112 };
 113
 114 union insn_t
 115 {
 116   itype_t itype;
 117   jtype_t jtype;
 118   rtype_t rtype;
 119   btype_t btype;
 120   ltype_t ltype;
 121   ftype_t ftype;
 122   uint32_t bits;
 123 };
 124
 125 #include <stdio.h>
 126 template <class T>
 127 class write_port_t
 128 {
 129 public:
 130   write_port_t(T& _t) : t(_t) {}
 131   T& operator = (const T& rhs)
 132   {
 133     return t = rhs;
 134   }
 135   operator T()
 136   {
 137     return t;
 138   }
 139 private:
 140   T& t;
 141 };
 142 template <class T, size_t N, bool zero_reg>
 143 class regfile_t
 144 {
 145 public:
 146   void reset()
 147   {
 148     memset(data, 0, sizeof(data));
 149   }
 150   write_port_t<T> write_port(size_t i)
 151   {
 152     return write_port_t<T>(data[i]);
 153   }
 154   const T& operator [] (size_t i) const
 155   {
 156     if (zero_reg)
 157       const_cast<T&>(data[0]) = 0;
 158     return data[i];
 159   }
 160 private:
 161   T data[N];
 162 };
 163
 164 #define throw_illegal_instruction \
 165   ({ if (utmode) throw trap_vector_illegal_instruction; \
 166      else throw trap_illegal_instruction; })
 167
 168 // helpful macros, etc
 169 #define RS1 XPR[insn.rtype.rs1]
 170 #define RS2 XPR[insn.rtype.rs2]
 171 #define RD XPR.write_port(insn.rtype.rd)
 172 #define RA XPR.write_port(1)
 173 #define FRS1 FPR[insn.ftype.rs1]
 174 #define FRS2 FPR[insn.ftype.rs2]
 175 #define FRS3 FPR[insn.ftype.rs3]
 176 #define FRD FPR.write_port(insn.ftype.rd)
 177 #define BIGIMM insn.ltype.bigimm
 178 #define SIMM insn.itype.imm12
 179 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 180 #define SHAMT (insn.itype.imm12 & 0x3F)
 181 #define SHAMTW (insn.itype.imm12 & 0x1F)
 182 #define TARGET insn.jtype.target
 183 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 184 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
 185 #define RM ({ int rm = insn.ftype.rm; \
 186               if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
 187               if(rm > 4) throw_illegal_instruction; \
 188               rm; })
 189
 190 #define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
 191 #define xpr64 (xprlen == 64)
 192 #define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
 193 #define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
 194 #define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
 195 #define require_vector \
 196   ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
 197     else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
 198   })
 199 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 200 #define set_fp_exceptions ({ set_fsr(fsr | \
 201                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 202                              softfloat_exceptionFlags = 0; })
 203
 204 #define sext32(x) ((sreg_t)(int32_t)(x))
 205 #define zext32(x) ((reg_t)(uint32_t)(x))
 206 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 207 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 208
 209 // RVC stuff
 210
 211 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
 212 #define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
 213 #define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
 214
 215 #define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
 216 #define CRD XPR.write_port(CRD_REGNUM)
 217 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
 218 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
 219 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
 220 #define CIMM5U ((insn.bits >> 5) & 0x1f)
 221 #define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
 222 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
 223 #define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
 224 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
 225
 226 static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
 227 #define rvc_rd_regmap rvc_rs1_regmap
 228 #define rvc_rs2b_regmap rvc_rs1_regmap
 229 static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
 230 #define CRDS XPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
 231 #define FCRDS FPR.write_port(rvc_rd_regmap[(insn.bits >> 13) & 0x7])
 232 #define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
 233 #define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 234 #define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
 235 #define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 236
 237 // vector stuff
 238 #define VL vl
 239
 240 #define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
 241 #define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
 242 #define UT_RD(idx) uts[idx]->XPR.write_port(insn.rtype.rd)
 243 #define UT_RA(idx) uts[idx]->XPR.write_port(1)
 244 #define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
 245 #define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
 246 #define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
 247 #define UT_FRD(idx) uts[idx]->FPR.write_port(insn.ftype.rd)
 248 #define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
 249               ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
 250
 251 #define UT_LOOP_START for (int i=0;i<VL; i++) {
 252 #define UT_LOOP_END }
 253 #define UT_LOOP_RS1 UT_RS1(i)
 254 #define UT_LOOP_RS2 UT_RS2(i)
 255 #define UT_LOOP_RD UT_RD(i)
 256 #define UT_LOOP_RA UT_RA(i)
 257 #define UT_LOOP_FRS1 UT_FRS1(i)
 258 #define UT_LOOP_FRS2 UT_FRS2(i)
 259 #define UT_LOOP_FRS3 UT_FRS3(i)
 260 #define UT_LOOP_FRD UT_FRD(i)
 261 #define UT_LOOP_RM UT_RM(i)
 262
 263 #define VEC_LOAD(dst, func, inc) \
 264   reg_t addr = RS1; \
 265   UT_LOOP_START \
 266     UT_LOOP_##dst = mmu.func(addr); \
 267     addr += inc; \
 268   UT_LOOP_END
 269
 270 #define VEC_STORE(src, func, inc) \
 271   reg_t addr = RS1; \
 272   UT_LOOP_START \
 273     mmu.func(addr, UT_LOOP_##src); \
 274     addr += inc; \
 275   UT_LOOP_END
 276
 277 enum vt_command_t
 278 {
 279   vt_command_stop,
 280 };
 281
 282 #endif