1 // See LICENSE for license details.
3 #ifndef _RISCV_DECODE_H
4 #define _RISCV_DECODE_H
6 #define __STDC_LIMIT_MACROS
13 typedef int int128_t
__attribute__((mode(TI
)));
14 typedef unsigned int uint128_t
__attribute__((mode(TI
)));
16 typedef int64_t sreg_t
;
17 typedef uint64_t reg_t
;
18 typedef uint64_t freg_t
;
20 const int OPCODE_BITS
= 7;
22 const int XPRID_BITS
= 5;
23 const int NXPR
= 1 << XPRID_BITS
;
25 const int FPR_BITS
= 64;
26 const int FPRID_BITS
= 5;
27 const int NFPR
= 1 << FPRID_BITS
;
29 const int IMM_BITS
= 12;
30 const int IMMLO_BITS
= 7;
31 const int TARGET_BITS
= 25;
32 const int FUNCT_BITS
= 3;
33 const int FUNCTR_BITS
= 7;
34 const int FFUNCT_BITS
= 2;
35 const int RM_BITS
= 3;
36 const int BIGIMM_BITS
= 20;
37 const int BRANCH_ALIGN_BITS
= 1;
38 const int JUMP_ALIGN_BITS
= 1;
46 #define FSR_RD_SHIFT 5
47 #define FSR_RD (0x7 << FSR_RD_SHIFT)
55 #define FSR_AEXC_SHIFT 0
56 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
57 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
58 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
59 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
60 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
61 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
63 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
65 // note: bit fields are in little-endian order
68 unsigned opcode
: OPCODE_BITS
;
69 unsigned funct
: FUNCT_BITS
;
70 signed imm12
: IMM_BITS
;
71 unsigned rs1
: XPRID_BITS
;
72 unsigned rd
: XPRID_BITS
;
77 unsigned opcode
: OPCODE_BITS
;
78 unsigned funct
: FUNCT_BITS
;
79 unsigned immlo
: IMMLO_BITS
;
80 unsigned rs2
: XPRID_BITS
;
81 unsigned rs1
: XPRID_BITS
;
82 signed immhi
: IMM_BITS
-IMMLO_BITS
;
87 unsigned opcode
: OPCODE_BITS
;
88 unsigned funct
: FUNCT_BITS
;
89 unsigned functr
: FUNCTR_BITS
;
90 unsigned rs2
: XPRID_BITS
;
91 unsigned rs1
: XPRID_BITS
;
92 unsigned rd
: XPRID_BITS
;
97 unsigned opcode
: OPCODE_BITS
;
98 signed bigimm
: BIGIMM_BITS
;
99 unsigned rd
: XPRID_BITS
;
104 unsigned opcode
: OPCODE_BITS
;
105 unsigned ffunct
: FFUNCT_BITS
;
106 unsigned rm
: RM_BITS
;
107 unsigned rs3
: FPRID_BITS
;
108 unsigned rs2
: FPRID_BITS
;
109 unsigned rs1
: FPRID_BITS
;
110 unsigned rd
: FPRID_BITS
;
127 write_port_t(T
& _t
) : t(_t
) {}
128 T
& operator = (const T
& rhs
)
139 template <class T
, size_t N
, bool zero_reg
>
145 memset(data
, 0, sizeof(data
));
147 write_port_t
<T
> write_port(size_t i
)
150 const_cast<T
&>(data
[0]) = 0;
151 return write_port_t
<T
>(data
[i
]);
153 const T
& operator [] (size_t i
) const
156 const_cast<T
&>(data
[0]) = 0;
163 // helpful macros, etc
164 #define MMU (*p->get_mmu())
165 #define RS1 p->get_state()->XPR[insn.rtype.rs1]
166 #define RS2 p->get_state()->XPR[insn.rtype.rs2]
167 #define RD p->get_state()->XPR.write_port(insn.rtype.rd)
168 #define FRS1 p->get_state()->FPR[insn.ftype.rs1]
169 #define FRS2 p->get_state()->FPR[insn.ftype.rs2]
170 #define FRS3 p->get_state()->FPR[insn.ftype.rs3]
171 #define FRD p->get_state()->FPR.write_port(insn.ftype.rd)
172 #define BIGIMM insn.ltype.bigimm
173 #define SIMM insn.itype.imm12
174 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
175 #define SHAMT (insn.itype.imm12 & 0x3F)
176 #define SHAMTW (insn.itype.imm12 & 0x1F)
177 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
178 #define JUMP_TARGET (pc + (BIGIMM << JUMP_ALIGN_BITS))
179 #define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
180 #define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
181 #define RM ({ int rm = insn.ftype.rm; \
182 if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \
183 if(rm > 4) throw trap_illegal_instruction(); \
186 #define xpr64 (xprlen == 64)
188 #define require_supervisor if(unlikely(!(p->get_state()->sr & SR_S))) throw trap_privileged_instruction()
189 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
190 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
191 #ifndef RISCV_ENABLE_FPU
192 # define require_fp throw trap_illegal_instruction()
194 # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
197 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
198 #define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \
199 (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
200 softfloat_exceptionFlags = 0; })
202 #define sext32(x) ((sreg_t)(int32_t)(x))
203 #define zext32(x) ((reg_t)(uint32_t)(x))
204 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
205 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
207 #define insn_length(x) \
208 (((x) & 0x03) < 0x03 ? 2 : \
209 ((x) & 0x1f) < 0x1f ? 4 : \
210 ((x) & 0x3f) < 0x3f ? 6 : \
214 do { if ((x) & 3 /* For now... */) \
215 throw trap_instruction_address_misaligned(); \