riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #define __STDC_LIMIT_MACROS
  11 #include <stdint.h>
  12 #include <string.h>
  13 #include "encoding.h"
  14 #include "config.h"
  15 #include "common.h"
  16 #include <cinttypes>
  17
  18 typedef int int128_t __attribute__((mode(TI)));
  19 typedef unsigned int uint128_t __attribute__((mode(TI)));
  20
  21 typedef int64_t sreg_t;
  22 typedef uint64_t reg_t;
  23 typedef uint64_t freg_t;
  24
  25 const int NXPR = 32;
  26 const int NFPR = 32;
  27
  28 #define FP_RD_NE  0
  29 #define FP_RD_0   1
  30 #define FP_RD_DN  2
  31 #define FP_RD_UP  3
  32 #define FP_RD_NMM 4
  33
  34 #define FSR_RD_SHIFT 5
  35 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  36
  37 #define FPEXC_NX 0x01
  38 #define FPEXC_UF 0x02
  39 #define FPEXC_OF 0x04
  40 #define FPEXC_DZ 0x08
  41 #define FPEXC_NV 0x10
  42
  43 #define FSR_AEXC_SHIFT 0
  44 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  45 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  46 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  47 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  48 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  49 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  50
  51 class insn_t
  52 {
  53 public:
  54   uint32_t bits() { return b; }
  55   int32_t i_imm() { return int32_t(b) >> 20; }
  56   int32_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
  57   int32_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
  58   int32_t u_imm() { return int32_t(b) >> 12 << 12; }
  59   int32_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
  60   uint32_t rd() { return x(7, 5); }
  61   uint32_t rs1() { return x(15, 5); }
  62   uint32_t rs2() { return x(20, 5); }
  63   uint32_t rs3() { return x(27, 5); }
  64   uint32_t rm() { return x(12, 3); }
  65   uint32_t csr() { return x(20, 12); }
  66 private:
  67   uint32_t b;
  68   uint32_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
  69   uint32_t xs(int lo, int len) { return int32_t(b) << (32-lo-len) >> (32-len); }
  70   uint32_t imm_sign() { return xs(31, 1); }
  71 };
  72
  73 template <class T, size_t N, bool zero_reg>
  74 class regfile_t
  75 {
  76 public:
  77   void reset()
  78   {
  79     memset(data, 0, sizeof(data));
  80   }
  81   void write(size_t i, T value)
  82   {
  83     data[i] = value;
  84     if (zero_reg)
  85       data[0] = 0;
  86   }
  87   const T& operator [] (size_t i) const
  88   {
  89     return data[i];
  90   }
  91 private:
  92   T data[N];
  93 };
  94
  95 // helpful macros, etc
  96 #define MMU (*p->get_mmu())
  97 #define STATE (*p->get_state())
  98 #define RS1 STATE.XPR[insn.rs1()]
  99 #define RS2 STATE.XPR[insn.rs2()]
 100 #define WRITE_RD(value) STATE.XPR.write(insn.rd(), value)
 101
 102 #ifdef RISCV_ENABLE_COMMITLOG
 103   #undef WRITE_RD
 104   #define WRITE_RD(value) ({ \
 105         reg_t wdata = value; /* value is a func with side-effects */ \
 106         STATE.log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
 107         STATE.XPR.write(insn.rd(), wdata); \
 108       })
 109 #endif
 110
 111 #define FRS1 STATE.FPR[insn.rs1()]
 112 #define FRS2 STATE.FPR[insn.rs2()]
 113 #define FRS3 STATE.FPR[insn.rs3()]
 114 #define WRITE_FRD(value) STATE.FPR.write(insn.rd(), value)
 115
 116 #ifdef RISCV_ENABLE_COMMITLOG
 117   #undef WRITE_FRD
 118   #define WRITE_FRD(value) ({ \
 119         freg_t wdata = value; /* value is a func with side-effects */ \
 120         STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
 121         STATE.FPR.write(insn.rd(), wdata); \
 122       })
 123 #endif
 124
 125
 126
 127 #define SHAMT (insn.i_imm() & 0x3F)
 128 #define BRANCH_TARGET (pc + insn.sb_imm())
 129 #define JUMP_TARGET (pc + insn.uj_imm())
 130 #define RM ({ int rm = insn.rm(); \
 131               if(rm == 7) rm = STATE.frm; \
 132               if(rm > 4) throw trap_illegal_instruction(); \
 133               rm; })
 134
 135 #define xpr64 (xprlen == 64)
 136
 137 #define require_supervisor if(unlikely(!(STATE.sr & SR_S))) throw trap_privileged_instruction()
 138 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
 139 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
 140 #ifndef RISCV_ENABLE_FPU
 141 # define require_fp throw trap_illegal_instruction()
 142 #else
 143 # define require_fp if(unlikely(!(STATE.sr & SR_EF))) throw trap_fp_disabled()
 144 #endif
 145 #define require_accelerator if(unlikely(!(STATE.sr & SR_EA))) throw trap_accelerator_disabled()
 146
 147 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 148 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
 149                              softfloat_exceptionFlags = 0; })
 150
 151 #define sext32(x) ((sreg_t)(int32_t)(x))
 152 #define zext32(x) ((reg_t)(uint32_t)(x))
 153 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 154 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 155
 156 #define insn_length(x) \
 157   (((x) & 0x03) < 0x03 ? 2 : \
 158    ((x) & 0x1f) < 0x1f ? 4 : \
 159    ((x) & 0x3f) < 0x3f ? 6 : \
 160    8)
 161
 162 #define set_pc(x) \
 163   do { if ((x) & 3 /* For now... */) \
 164          throw trap_instruction_address_misaligned(); \
 165        npc = sext_xprlen(x); \
 166      } while(0)
 167
 168 #define validate_csr(which, write) ({ \
 169   unsigned my_priv = (STATE.sr & SR_S) ? 1 : 0; \
 170   unsigned read_priv = ((which) >> 10) & 3; \
 171   unsigned write_priv = (((which) >> 8) & 3); \
 172   if (read_priv == 3) read_priv = write_priv, write_priv = -1; \
 173   if (my_priv < ((write) ? write_priv : read_priv)) \
 174     throw trap_privileged_instruction(); \
 175   (which); })
 176
 177 #endif