riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6 #include "common.h"
   7 #include "config.h"
   8
   9 typedef int int128_t __attribute__((mode(TI)));
  10 typedef unsigned int uint128_t __attribute__((mode(TI)));
  11
  12 typedef int64_t sreg_t;
  13 typedef uint64_t reg_t;
  14 typedef uint64_t freg_t;
  15
  16 const int OPCODE_BITS = 7;
  17
  18 const int XPRID_BITS = 5;
  19 const int NXPR = 1 << XPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int IMMLO_BITS = 7;
  27 const int TARGET_BITS = 25;
  28 const int FUNCT_BITS = 3;
  29 const int FUNCTR_BITS = 7;
  30 const int FFUNCT_BITS = 2;
  31 const int RM_BITS = 3;
  32 const int BIGIMM_BITS = 20;
  33 const int BRANCH_ALIGN_BITS = 1;
  34 const int JUMP_ALIGN_BITS = 1;
  35
  36 #define SR_ET    0x0000000000000001ULL
  37 #define SR_EF    0x0000000000000002ULL
  38 #define SR_EV    0x0000000000000004ULL
  39 #define SR_EC    0x0000000000000008ULL
  40 #define SR_PS    0x0000000000000010ULL
  41 #define SR_S     0x0000000000000020ULL
  42 #define SR_UX    0x0000000000000040ULL
  43 #define SR_SX    0x0000000000000080ULL
  44 #define SR_IM    0x000000000000FF00ULL
  45 #define SR_VM    0x0000000000010000ULL
  46 #define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM|SR_VM)
  47 #define SR_IM_SHIFT 8
  48 #define IPI_IRQ 5
  49 #define TIMER_IRQ 7
  50
  51 #define FP_RD_NE  0
  52 #define FP_RD_0   1
  53 #define FP_RD_DN  2
  54 #define FP_RD_UP  3
  55 #define FP_RD_NMM 4
  56
  57 #define FSR_RD_SHIFT 5
  58 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  59
  60 #define FPEXC_NX 0x01
  61 #define FPEXC_UF 0x02
  62 #define FPEXC_OF 0x04
  63 #define FPEXC_DZ 0x08
  64 #define FPEXC_NV 0x10
  65
  66 #define FSR_AEXC_SHIFT 0
  67 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  68 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  69 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  70 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  71 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  72 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  73
  74 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  75
  76 // note: bit fields are in little-endian order
  77 struct itype_t
  78 {
  79   unsigned opcode : OPCODE_BITS;
  80   unsigned funct : FUNCT_BITS;
  81   signed imm12 : IMM_BITS;
  82   unsigned rs1 : XPRID_BITS;
  83   unsigned rd : XPRID_BITS;
  84 };
  85
  86 struct btype_t
  87 {
  88   unsigned opcode : OPCODE_BITS;
  89   unsigned funct : FUNCT_BITS;
  90   unsigned immlo : IMMLO_BITS;
  91   unsigned rs2 : XPRID_BITS;
  92   unsigned rs1 : XPRID_BITS;
  93   signed immhi : IMM_BITS-IMMLO_BITS;
  94 };
  95
  96 struct jtype_t
  97 {
  98   unsigned jump_opcode : OPCODE_BITS;
  99   signed target : TARGET_BITS;
 100 };
 101
 102 struct rtype_t
 103 {
 104   unsigned opcode : OPCODE_BITS;
 105   unsigned funct : FUNCT_BITS;
 106   unsigned functr : FUNCTR_BITS;
 107   unsigned rs2 : XPRID_BITS;
 108   unsigned rs1 : XPRID_BITS;
 109   unsigned rd : XPRID_BITS;
 110 };
 111
 112 struct ltype_t
 113 {
 114   unsigned opcode : OPCODE_BITS;
 115   unsigned bigimm : BIGIMM_BITS;
 116   unsigned rd : XPRID_BITS;
 117 };
 118
 119 struct ftype_t
 120 {
 121   unsigned opcode : OPCODE_BITS;
 122   unsigned ffunct : FFUNCT_BITS;
 123   unsigned rm : RM_BITS;
 124   unsigned rs3 : FPRID_BITS;
 125   unsigned rs2 : FPRID_BITS;
 126   unsigned rs1 : FPRID_BITS;
 127   unsigned rd  : FPRID_BITS;
 128 };
 129
 130 union insn_t
 131 {
 132   itype_t itype;
 133   jtype_t jtype;
 134   rtype_t rtype;
 135   btype_t btype;
 136   ltype_t ltype;
 137   ftype_t ftype;
 138   uint32_t bits;
 139 };
 140
 141 #include <stdio.h>
 142 class do_writeback
 143 {
 144 public:
 145   do_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 146
 147   const do_writeback& operator = (reg_t rhs)
 148   {
 149 #if 0
 150     printf("R[%x] <= %llx\n",rd,(long long)rhs);
 151 #endif
 152     rf[rd] = rhs;
 153     rf[0] = 0;
 154     return *this;
 155   }
 156
 157   operator reg_t() { return rf[rd]; }
 158
 159 private:
 160   reg_t* rf;
 161   int rd;
 162 };
 163
 164 #define throw_illegal_instruction \
 165   ({ if (utmode) throw trap_vector_illegal_instruction; \
 166      else throw trap_illegal_instruction; })
 167
 168 // helpful macros, etc
 169 #define RS1 XPR[insn.rtype.rs1]
 170 #define RS2 XPR[insn.rtype.rs2]
 171 #define RD do_writeback(XPR,insn.rtype.rd)
 172 #define RA do_writeback(XPR,1)
 173 #define FRS1 FPR[insn.ftype.rs1]
 174 #define FRS2 FPR[insn.ftype.rs2]
 175 #define FRS3 FPR[insn.ftype.rs3]
 176 #define FRD FPR[insn.ftype.rd]
 177 #define BIGIMM insn.ltype.bigimm
 178 #define SIMM insn.itype.imm12
 179 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 180 #define SHAMT (insn.itype.imm12 & 0x3F)
 181 #define SHAMTW (insn.itype.imm12 & 0x1F)
 182 #define TARGET insn.jtype.target
 183 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 184 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
 185 #define RM ({ int rm = insn.ftype.rm; \
 186               if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
 187               if(rm > 4) throw_illegal_instruction; \
 188               rm; })
 189
 190 #define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
 191 #define xpr64 (xprlen == 64)
 192 #define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
 193 #define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
 194 #define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
 195 #define require_vector \
 196   ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
 197     else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
 198   })
 199 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 200 #define set_fp_exceptions ({ set_fsr(fsr | \
 201                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 202                              softfloat_exceptionFlags = 0; })
 203
 204 #define sext32(x) ((sreg_t)(int32_t)(x))
 205 #define zext32(x) ((reg_t)(uint32_t)(x))
 206 #define sext_xprlen(x) ((sreg_t(x) << (64-xprlen)) >> (64-xprlen))
 207 #define zext_xprlen(x) ((reg_t(x) << (64-xprlen)) >> (64-xprlen))
 208
 209 #ifndef RISCV_ENABLE_RVC
 210 # define set_pc(x) \
 211   do { if((x) & (sizeof(insn_t)-1)) \
 212        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
 213        npc = (x); \
 214      } while(0)
 215 #else
 216 # define set_pc(x) \
 217   do { if((x) & ((sr & SR_EC) ? 1 : 3)) \
 218        { badvaddr = (x); throw trap_instruction_address_misaligned; } \
 219        npc = (x); \
 220      } while(0)
 221 #endif
 222
 223 // RVC stuff
 224
 225 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
 226 #define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
 227 #define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
 228
 229 #define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
 230 #define CRD do_writeback(XPR, CRD_REGNUM)
 231 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
 232 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
 233 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
 234 #define CIMM5U ((insn.bits >> 5) & 0x1f)
 235 #define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
 236 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
 237 #define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
 238 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
 239
 240 static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
 241 #define rvc_rd_regmap rvc_rs1_regmap
 242 #define rvc_rs2b_regmap rvc_rs1_regmap
 243 static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
 244 #define CRDS XPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
 245 #define FCRDS FPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
 246 #define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
 247 #define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 248 #define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
 249 #define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 250
 251 // vector stuff
 252 #define VL vl
 253
 254 #define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
 255 #define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
 256 #define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd)
 257 #define UT_RA(idx) do_writeback(uts[idx]->XPR,1)
 258 #define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
 259 #define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
 260 #define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
 261 #define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd]
 262 #define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
 263               ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
 264
 265 #define UT_LOOP_START for (int i=0;i<VL; i++) {
 266 #define UT_LOOP_END }
 267 #define UT_LOOP_RS1 UT_RS1(i)
 268 #define UT_LOOP_RS2 UT_RS2(i)
 269 #define UT_LOOP_RD UT_RD(i)
 270 #define UT_LOOP_RA UT_RA(i)
 271 #define UT_LOOP_FRS1 UT_FRS1(i)
 272 #define UT_LOOP_FRS2 UT_FRS2(i)
 273 #define UT_LOOP_FRS3 UT_FRS3(i)
 274 #define UT_LOOP_FRD UT_FRD(i)
 275 #define UT_LOOP_RM UT_RM(i)
 276
 277 #define VEC_LOAD(dst, func, inc) \
 278   reg_t addr = RS1; \
 279   UT_LOOP_START \
 280     UT_LOOP_##dst = mmu.func(addr); \
 281     addr += inc; \
 282   UT_LOOP_END
 283
 284 #define VEC_STORE(src, func, inc) \
 285   reg_t addr = RS1; \
 286   UT_LOOP_START \
 287     mmu.func(addr, UT_LOOP_##src); \
 288     addr += inc; \
 289   UT_LOOP_END
 290
 291 enum vt_command_t
 292 {
 293   vt_command_stop,
 294 };
 295
 296 #endif