riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #define __STDC_LIMIT_MACROS
  11 #include <stdint.h>
  12 #include <string.h>
  13 #include "encoding.h"
  14 #include "config.h"
  15 #include "common.h"
  16 #include <cinttypes>
  17
  18 typedef int int128_t __attribute__((mode(TI)));
  19 typedef unsigned int uint128_t __attribute__((mode(TI)));
  20
  21 typedef int64_t sreg_t;
  22 typedef uint64_t reg_t;
  23 typedef uint64_t freg_t;
  24
  25 const int NXPR = 32;
  26 const int NFPR = 32;
  27
  28 #define FP_RD_NE  0
  29 #define FP_RD_0   1
  30 #define FP_RD_DN  2
  31 #define FP_RD_UP  3
  32 #define FP_RD_NMM 4
  33
  34 #define FSR_RD_SHIFT 5
  35 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  36
  37 #define FPEXC_NX 0x01
  38 #define FPEXC_UF 0x02
  39 #define FPEXC_OF 0x04
  40 #define FPEXC_DZ 0x08
  41 #define FPEXC_NV 0x10
  42
  43 #define FSR_AEXC_SHIFT 0
  44 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  45 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  46 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  47 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  48 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  49 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  50
  51 class insn_t
  52 {
  53 public:
  54   uint32_t bits() { return b; }
  55   reg_t i_imm() { return int64_t(int32_t(b) >> 20); }
  56   reg_t s_imm() { return x(7, 5) | (x(25, 7) << 5) | (imm_sign() << 12); }
  57   reg_t sb_imm() { return (x(8, 4) << 1) | (x(25,6) << 5) | (x(7,1) << 11) | (imm_sign() << 12); }
  58   reg_t u_imm() { return int64_t(int32_t(b) >> 12 << 12); }
  59   reg_t uj_imm() { return (x(21, 10) << 1) | (x(20, 1) << 11) | (x(12, 8) << 12) | (imm_sign() << 20); }
  60   uint32_t rd() { return x(7, 5); }
  61   uint32_t rs1() { return x(15, 5); }
  62   uint32_t rs2() { return x(20, 5); }
  63   uint32_t rs3() { return x(27, 5); }
  64   uint32_t rm() { return x(12, 3); }
  65 private:
  66   uint32_t b;
  67   reg_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
  68   reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
  69 };
  70
  71 template <class T, size_t N, bool zero_reg>
  72 class regfile_t
  73 {
  74 public:
  75   void reset()
  76   {
  77     memset(data, 0, sizeof(data));
  78   }
  79   void write(size_t i, T value)
  80   {
  81     data[i] = value;
  82   }
  83   const T& operator [] (size_t i) const
  84   {
  85     if (zero_reg)
  86       const_cast<T&>(data[0]) = 0;
  87     return data[i];
  88   }
  89 private:
  90   T data[N];
  91 };
  92
  93 // helpful macros, etc
  94 #define MMU (*p->get_mmu())
  95 #define RS1 p->get_state()->XPR[insn.rs1()]
  96 #define RS2 p->get_state()->XPR[insn.rs2()]
  97 #define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
  98
  99 #ifdef RISCV_ENABLE_COMMITLOG
 100   #undef WRITE_RD
 101   #define WRITE_RD(value) ({ \
 102         bool in_spvr = p->get_state()->sr & SR_S; \
 103         reg_t wdata = value; /* value is a func with side-effects */ \
 104         if (!in_spvr) \
 105           fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
 106         p->get_state()->XPR.write(insn.rd(), wdata); \
 107       })
 108 #endif
 109
 110 #define FRS1 p->get_state()->FPR[insn.rs1()]
 111 #define FRS2 p->get_state()->FPR[insn.rs2()]
 112 #define FRS3 p->get_state()->FPR[insn.rs3()]
 113 #define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
 114
 115 #ifdef RISCV_ENABLE_COMMITLOG
 116   #undef WRITE_FRD
 117   #define WRITE_FRD(value) ({ \
 118         bool in_spvr = p->get_state()->sr & SR_S; \
 119         freg_t wdata = value; /* value is a func with side-effects */ \
 120         if (!in_spvr) \
 121           fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
 122         p->get_state()->FPR.write(insn.rd(), wdata); \
 123       })
 124 #endif
 125
 126
 127
 128 #define SHAMT (insn.i_imm() & 0x3F)
 129 #define BRANCH_TARGET (pc + insn.sb_imm())
 130 #define JUMP_TARGET (pc + insn.uj_imm())
 131 #define RM ({ int rm = insn.rm(); \
 132               if(rm == 7) rm = p->get_state()->frm; \
 133               if(rm > 4) throw trap_illegal_instruction(); \
 134               rm; })
 135
 136 #define xpr64 (xprlen == 64)
 137
 138 #define require_supervisor if(unlikely(!(p->get_state()->sr & SR_S))) throw trap_privileged_instruction()
 139 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
 140 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
 141 #ifndef RISCV_ENABLE_FPU
 142 # define require_fp throw trap_illegal_instruction()
 143 #else
 144 # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
 145 #endif
 146 #define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled()
 147
 148 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 149 #define set_fp_exceptions ({ p->get_state()->fflags |= softfloat_exceptionFlags; \
 150                              softfloat_exceptionFlags = 0; })
 151
 152 #define sext32(x) ((sreg_t)(int32_t)(x))
 153 #define zext32(x) ((reg_t)(uint32_t)(x))
 154 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 155 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 156
 157 #define insn_length(x) \
 158   (((x) & 0x03) < 0x03 ? 2 : \
 159    ((x) & 0x1f) < 0x1f ? 4 : \
 160    ((x) & 0x3f) < 0x3f ? 6 : \
 161    8)
 162
 163 #define set_pc(x) \
 164   do { if ((x) & 3 /* For now... */) \
 165          throw trap_instruction_address_misaligned(); \
 166        npc = (x); \
 167      } while(0)
 168
 169 #define validate_csr(which, write) ({ \
 170   int read_priv = ((which) >> 10) & 3; \
 171   int write_priv = ((which) >> 8) & 3; \
 172   if (read_priv > 0 || (write_priv > 0 && (write))) require_supervisor; \
 173   (which); })
 174
 175 #endif