riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #define __STDC_LIMIT_MACROS
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include "pcr.h"
  10 #include "config.h"
  11
  12 typedef int int128_t __attribute__((mode(TI)));
  13 typedef unsigned int uint128_t __attribute__((mode(TI)));
  14
  15 typedef int64_t sreg_t;
  16 typedef uint64_t reg_t;
  17 typedef uint64_t freg_t;
  18
  19 const int OPCODE_BITS = 7;
  20
  21 const int XPRID_BITS = 5;
  22 const int NXPR = 1 << XPRID_BITS;
  23
  24 const int FPR_BITS = 64;
  25 const int FPRID_BITS = 5;
  26 const int NFPR = 1 << FPRID_BITS;
  27
  28 const int IMM_BITS = 12;
  29 const int IMMLO_BITS = 7;
  30 const int TARGET_BITS = 25;
  31 const int FUNCT_BITS = 3;
  32 const int FUNCTR_BITS = 7;
  33 const int FFUNCT_BITS = 2;
  34 const int RM_BITS = 3;
  35 const int BIGIMM_BITS = 20;
  36 const int BRANCH_ALIGN_BITS = 1;
  37 const int JUMP_ALIGN_BITS = 1;
  38
  39 #define FP_RD_NE  0
  40 #define FP_RD_0   1
  41 #define FP_RD_DN  2
  42 #define FP_RD_UP  3
  43 #define FP_RD_NMM 4
  44
  45 #define FSR_RD_SHIFT 5
  46 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  47
  48 #define FPEXC_NX 0x01
  49 #define FPEXC_UF 0x02
  50 #define FPEXC_OF 0x04
  51 #define FPEXC_DZ 0x08
  52 #define FPEXC_NV 0x10
  53
  54 #define FSR_AEXC_SHIFT 0
  55 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  56 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  57 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  58 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  59 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  60 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  61
  62 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  63
  64 // note: bit fields are in little-endian order
  65 struct itype_t
  66 {
  67   unsigned opcode : OPCODE_BITS;
  68   unsigned funct : FUNCT_BITS;
  69   signed imm12 : IMM_BITS;
  70   unsigned rs1 : XPRID_BITS;
  71   unsigned rd : XPRID_BITS;
  72 };
  73
  74 struct btype_t
  75 {
  76   unsigned opcode : OPCODE_BITS;
  77   unsigned funct : FUNCT_BITS;
  78   unsigned immlo : IMMLO_BITS;
  79   unsigned rs2 : XPRID_BITS;
  80   unsigned rs1 : XPRID_BITS;
  81   signed immhi : IMM_BITS-IMMLO_BITS;
  82 };
  83
  84 struct jtype_t
  85 {
  86   unsigned jump_opcode : OPCODE_BITS;
  87   signed target : TARGET_BITS;
  88 };
  89
  90 struct rtype_t
  91 {
  92   unsigned opcode : OPCODE_BITS;
  93   unsigned funct : FUNCT_BITS;
  94   unsigned functr : FUNCTR_BITS;
  95   unsigned rs2 : XPRID_BITS;
  96   unsigned rs1 : XPRID_BITS;
  97   unsigned rd : XPRID_BITS;
  98 };
  99
 100 struct ltype_t
 101 {
 102   unsigned opcode : OPCODE_BITS;
 103   unsigned bigimm : BIGIMM_BITS;
 104   unsigned rd : XPRID_BITS;
 105 };
 106
 107 struct ftype_t
 108 {
 109   unsigned opcode : OPCODE_BITS;
 110   unsigned ffunct : FFUNCT_BITS;
 111   unsigned rm : RM_BITS;
 112   unsigned rs3 : FPRID_BITS;
 113   unsigned rs2 : FPRID_BITS;
 114   unsigned rs1 : FPRID_BITS;
 115   unsigned rd  : FPRID_BITS;
 116 };
 117
 118 union insn_t
 119 {
 120   itype_t itype;
 121   jtype_t jtype;
 122   rtype_t rtype;
 123   btype_t btype;
 124   ltype_t ltype;
 125   ftype_t ftype;
 126   uint_fast32_t bits;
 127 };
 128
 129 template <class T>
 130 class write_port_t
 131 {
 132 public:
 133   write_port_t(T& _t) : t(_t) {}
 134   T& operator = (const T& rhs)
 135   {
 136     return t = rhs;
 137   }
 138   operator T()
 139   {
 140     return t;
 141   }
 142 private:
 143   T& t;
 144 };
 145 template <class T, size_t N, bool zero_reg>
 146 class regfile_t
 147 {
 148 public:
 149   void reset()
 150   {
 151     memset(data, 0, sizeof(data));
 152   }
 153   write_port_t<T> write_port(size_t i)
 154   {
 155     if (zero_reg)
 156       const_cast<T&>(data[0]) = 0;
 157     return write_port_t<T>(data[i]);
 158   }
 159   const T& operator [] (size_t i) const
 160   {
 161     if (zero_reg)
 162       const_cast<T&>(data[0]) = 0;
 163     return data[i];
 164   }
 165 private:
 166   T data[N];
 167 };
 168
 169 // helpful macros, etc
 170 #define RS1 XPR[insn.rtype.rs1]
 171 #define RS2 XPR[insn.rtype.rs2]
 172 #define RD XPR.write_port(insn.rtype.rd)
 173 #define RA XPR.write_port(1)
 174 #define FRS1 FPR[insn.ftype.rs1]
 175 #define FRS2 FPR[insn.ftype.rs2]
 176 #define FRS3 FPR[insn.ftype.rs3]
 177 #define FRD FPR.write_port(insn.ftype.rd)
 178 #define BIGIMM insn.ltype.bigimm
 179 #define SIMM insn.itype.imm12
 180 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 181 #define SHAMT (insn.itype.imm12 & 0x3F)
 182 #define SHAMTW (insn.itype.imm12 & 0x1F)
 183 #define TARGET insn.jtype.target
 184 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 185 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
 186 #define ITYPE_EADDR sext_xprlen(RS1 + SIMM)
 187 #define BTYPE_EADDR sext_xprlen(RS1 + BIMM)
 188 #define RM ({ int rm = insn.ftype.rm; \
 189               if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
 190               if(rm > 4) throw trap_illegal_instruction; \
 191               rm; })
 192
 193 #define xpr64 (xprlen == 64)
 194
 195 #define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
 196 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction
 197 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction
 198 #ifndef RISCV_ENABLE_FPU
 199 # define require_fp throw trap_illegal_instruction
 200 #else
 201 # define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
 202 #endif
 203
 204 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 205 #define set_fp_exceptions ({ set_fsr(fsr | \
 206                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 207                              softfloat_exceptionFlags = 0; })
 208
 209 #define sext32(x) ((sreg_t)(int32_t)(x))
 210 #define zext32(x) ((reg_t)(uint32_t)(x))
 211 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 212 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 213
 214 #define insn_length(x) \
 215   (((x) & 0x03) < 0x03 ? 2 : \
 216    ((x) & 0x1f) < 0x1f ? 4 : \
 217    ((x) & 0x3f) < 0x3f ? 6 : \
 218    8)
 219
 220 #define set_pc(x) \
 221   do { if ((x) & 3 /* For now... */) \
 222          throw trap_instruction_address_misaligned; \
 223        npc = (x); \
 224      } while(0)
 225
 226 #endif