riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #define __STDC_LIMIT_MACROS
  11 #include <stdint.h>
  12 #include <string.h>
  13 #include "pcr.h"
  14 #include "config.h"
  15 #include "common.h"
  16 #include <cinttypes>
  17
  18 typedef int int128_t __attribute__((mode(TI)));
  19 typedef unsigned int uint128_t __attribute__((mode(TI)));
  20
  21 typedef int64_t sreg_t;
  22 typedef uint64_t reg_t;
  23 typedef uint64_t freg_t;
  24
  25 const int NXPR = 32;
  26 const int NFPR = 32;
  27
  28 #define FP_RD_NE  0
  29 #define FP_RD_0   1
  30 #define FP_RD_DN  2
  31 #define FP_RD_UP  3
  32 #define FP_RD_NMM 4
  33
  34 #define FSR_RD_SHIFT 5
  35 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  36
  37 #define FPEXC_NX 0x01
  38 #define FPEXC_UF 0x02
  39 #define FPEXC_OF 0x04
  40 #define FPEXC_DZ 0x08
  41 #define FPEXC_NV 0x10
  42
  43 #define FSR_AEXC_SHIFT 0
  44 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  45 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  46 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  47 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  48 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  49 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  50
  51 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  52
  53 class insn_t
  54 {
  55 public:
  56   uint32_t bits() { return b; }
  57   reg_t i_imm() { return int64_t(int32_t(b) >> 20); }
  58   reg_t s_imm() { return x(7, 5) | (x(25, 7) << 5) | (imm_sign() << 12); }
  59   reg_t sb_imm() { return (x(8, 4) << 1) | (x(25,6) << 5) | (x(7,1) << 11) | (imm_sign() << 12); }
  60   reg_t u_imm() { return int64_t(int32_t(b) >> 12 << 12); }
  61   reg_t uj_imm() { return (x(21, 10) << 1) | (x(20, 1) << 11) | (x(12, 8) << 12) | (imm_sign() << 20); }
  62   uint32_t rd() { return x(7, 5); }
  63   uint32_t rs1() { return x(15, 5); }
  64   uint32_t rs2() { return x(20, 5); }
  65   uint32_t rs3() { return x(27, 5); }
  66   uint32_t rm() { return x(12, 3); }
  67 private:
  68   uint32_t b;
  69   reg_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
  70   reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
  71 };
  72
  73 template <class T, size_t N, bool zero_reg>
  74 class regfile_t
  75 {
  76 public:
  77   void reset()
  78   {
  79     memset(data, 0, sizeof(data));
  80   }
  81   void write(size_t i, T value)
  82   {
  83     data[i] = value;
  84   }
  85   const T& operator [] (size_t i) const
  86   {
  87     if (zero_reg)
  88       const_cast<T&>(data[0]) = 0;
  89     return data[i];
  90   }
  91 private:
  92   T data[N];
  93 };
  94
  95 // helpful macros, etc
  96 #define MMU (*p->get_mmu())
  97 #define RS1 p->get_state()->XPR[insn.rs1()]
  98 #define RS2 p->get_state()->XPR[insn.rs2()]
  99 #define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
 100
 101 #ifdef RISCV_ENABLE_COMMITLOG
 102   #undef WRITE_RD
 103   #define WRITE_RD(value) ({ \
 104         bool in_spvr = p->get_state()->sr & SR_S; \
 105         reg_t wdata = value; /* value is a func with side-effects */ \
 106         if (!in_spvr) \
 107           fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
 108         p->get_state()->XPR.write(insn.rd(), wdata); \
 109       })
 110 #endif
 111
 112 #define FRS1 p->get_state()->FPR[insn.rs1()]
 113 #define FRS2 p->get_state()->FPR[insn.rs2()]
 114 #define FRS3 p->get_state()->FPR[insn.rs3()]
 115 #define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
 116
 117 #ifdef RISCV_ENABLE_COMMITLOG
 118   #undef WRITE_FRD
 119   #define WRITE_FRD(value) ({ \
 120         bool in_spvr = p->get_state()->sr & SR_S; \
 121         freg_t wdata = value; /* value is a func with side-effects */ \
 122         if (!in_spvr) \
 123           fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
 124         p->get_state()->FPR.write(insn.rd(), wdata); \
 125       })
 126 #endif
 127
 128
 129
 130 #define SHAMT (insn.i_imm() & 0x3F)
 131 #define BRANCH_TARGET (pc + insn.sb_imm())
 132 #define JUMP_TARGET (pc + insn.uj_imm())
 133 #define RM ({ int rm = insn.rm(); \
 134               if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \
 135               if(rm > 4) throw trap_illegal_instruction(); \
 136               rm; })
 137
 138 #define xpr64 (xprlen == 64)
 139
 140 #define require_supervisor if(unlikely(!(p->get_state()->sr & SR_S))) throw trap_privileged_instruction()
 141 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
 142 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
 143 #ifndef RISCV_ENABLE_FPU
 144 # define require_fp throw trap_illegal_instruction()
 145 #else
 146 # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
 147 #endif
 148 #define require_accelerator if(unlikely(!(p->get_state()->sr & SR_EA))) throw trap_accelerator_disabled()
 149
 150 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 151 #define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \
 152                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 153                              softfloat_exceptionFlags = 0; })
 154
 155 #define sext32(x) ((sreg_t)(int32_t)(x))
 156 #define zext32(x) ((reg_t)(uint32_t)(x))
 157 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 158 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 159
 160 #define insn_length(x) \
 161   (((x) & 0x03) < 0x03 ? 2 : \
 162    ((x) & 0x1f) < 0x1f ? 4 : \
 163    ((x) & 0x3f) < 0x3f ? 6 : \
 164    8)
 165
 166 #define set_pc(x) \
 167   do { if ((x) & 3 /* For now... */) \
 168          throw trap_instruction_address_misaligned(); \
 169        npc = (x); \
 170      } while(0)
 171
 172 #endif