riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #define __STDC_LIMIT_MACROS
  11 #include <stdint.h>
  12 #include <string.h>
  13 #include "pcr.h"
  14 #include "config.h"
  15 #include "common.h"
  16
  17 typedef int int128_t __attribute__((mode(TI)));
  18 typedef unsigned int uint128_t __attribute__((mode(TI)));
  19
  20 typedef int64_t sreg_t;
  21 typedef uint64_t reg_t;
  22 typedef uint64_t freg_t;
  23
  24 const int NXPR = 32;
  25 const int NFPR = 32;
  26
  27 #define FP_RD_NE  0
  28 #define FP_RD_0   1
  29 #define FP_RD_DN  2
  30 #define FP_RD_UP  3
  31 #define FP_RD_NMM 4
  32
  33 #define FSR_RD_SHIFT 5
  34 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  35
  36 #define FPEXC_NX 0x01
  37 #define FPEXC_UF 0x02
  38 #define FPEXC_OF 0x04
  39 #define FPEXC_DZ 0x08
  40 #define FPEXC_NV 0x10
  41
  42 #define FSR_AEXC_SHIFT 0
  43 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  44 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  45 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  46 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  47 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  48 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  49
  50 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  51
  52 class insn_t
  53 {
  54 public:
  55   uint32_t bits() { return b; }
  56   reg_t i_imm() { return int64_t(int32_t(b) >> 20); }
  57   reg_t s_imm() { return x(7, 5) | (x(25, 7) << 5) | (imm_sign() << 12); }
  58   reg_t sb_imm() { return (x(8, 4) << 1) | (x(25,6) << 5) | (x(7,1) << 11) | (imm_sign() << 12); }
  59   reg_t u_imm() { return int64_t(int32_t(b) >> 12 << 12); }
  60   reg_t uj_imm() { return (x(21, 10) << 1) | (x(20, 1) << 11) | (x(12, 8) << 12) | (imm_sign() << 20); }
  61   uint32_t rd() { return x(7, 5); }
  62   uint32_t rs1() { return x(15, 5); }
  63   uint32_t rs2() { return x(20, 5); }
  64   uint32_t rs3() { return x(27, 5); }
  65   uint32_t rm() { return x(12, 3); }
  66 private:
  67   uint32_t b;
  68   reg_t x(int lo, int len) { return b << (32-lo-len) >> (32-len); }
  69   reg_t imm_sign() { return int64_t(int32_t(b) >> 31); }
  70 };
  71
  72 template <class T>
  73 class write_port_t
  74 {
  75 public:
  76   write_port_t(T& _t) : t(_t) {}
  77   T& operator = (const T& rhs)
  78   {
  79     return t = rhs;
  80   }
  81   operator T()
  82   {
  83     return t;
  84   }
  85 private:
  86   T& t;
  87 };
  88 template <class T, size_t N, bool zero_reg>
  89 class regfile_t
  90 {
  91 public:
  92   void reset()
  93   {
  94     memset(data, 0, sizeof(data));
  95   }
  96   write_port_t<T> write_port(size_t i)
  97   {
  98     if (zero_reg)
  99       const_cast<T&>(data[0]) = 0;
 100     return write_port_t<T>(data[i]);
 101   }
 102   const T& operator [] (size_t i) const
 103   {
 104     if (zero_reg)
 105       const_cast<T&>(data[0]) = 0;
 106     return data[i];
 107   }
 108 private:
 109   T data[N];
 110 };
 111
 112 // helpful macros, etc
 113 #define MMU (*p->get_mmu())
 114 #define RS1 p->get_state()->XPR[insn.rs1()]
 115 #define RS2 p->get_state()->XPR[insn.rs2()]
 116 #define RD p->get_state()->XPR.write_port(insn.rd())
 117 #define FRS1 p->get_state()->FPR[insn.rs1()]
 118 #define FRS2 p->get_state()->FPR[insn.rs2()]
 119 #define FRS3 p->get_state()->FPR[insn.rs3()]
 120 #define FRD p->get_state()->FPR.write_port(insn.rd())
 121 #define SHAMT (insn.i_imm() & 0x3F)
 122 #define BRANCH_TARGET (pc + insn.sb_imm())
 123 #define JUMP_TARGET (pc + insn.uj_imm())
 124 #define RM ({ int rm = insn.rm(); \
 125               if(rm == 7) rm = (p->get_state()->fsr & FSR_RD) >> FSR_RD_SHIFT; \
 126               if(rm > 4) throw trap_illegal_instruction(); \
 127               rm; })
 128
 129 #define xpr64 (xprlen == 64)
 130
 131 #define require_supervisor if(unlikely(!(p->get_state()->sr & SR_S))) throw trap_privileged_instruction()
 132 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
 133 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
 134 #ifndef RISCV_ENABLE_FPU
 135 # define require_fp throw trap_illegal_instruction()
 136 #else
 137 # define require_fp if(unlikely(!(p->get_state()->sr & SR_EF))) throw trap_fp_disabled()
 138 #endif
 139
 140 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 141 #define set_fp_exceptions ({ p->set_fsr(p->get_state()->fsr | \
 142                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 143                              softfloat_exceptionFlags = 0; })
 144
 145 #define sext32(x) ((sreg_t)(int32_t)(x))
 146 #define zext32(x) ((reg_t)(uint32_t)(x))
 147 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 148 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 149
 150 #define insn_length(x) \
 151   (((x) & 0x03) < 0x03 ? 2 : \
 152    ((x) & 0x1f) < 0x1f ? 4 : \
 153    ((x) & 0x3f) < 0x3f ? 6 : \
 154    8)
 155
 156 #define set_pc(x) \
 157   do { if ((x) & 3 /* For now... */) \
 158          throw trap_instruction_address_misaligned(); \
 159        npc = (x); \
 160      } while(0)
 161
 162 #endif