riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #include <cstdint>
  11 #include <string.h>
  12 #include "encoding.h"
  13 #include "config.h"
  14 #include "common.h"
  15 #include <cinttypes>
  16
  17 typedef int64_t sreg_t;
  18 typedef uint64_t reg_t;
  19 typedef uint64_t freg_t;
  20
  21 const int NXPR = 32;
  22 const int NFPR = 32;
  23
  24 #define FP_RD_NE  0
  25 #define FP_RD_0   1
  26 #define FP_RD_DN  2
  27 #define FP_RD_UP  3
  28 #define FP_RD_NMM 4
  29
  30 #define FSR_RD_SHIFT 5
  31 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  32
  33 #define FPEXC_NX 0x01
  34 #define FPEXC_UF 0x02
  35 #define FPEXC_OF 0x04
  36 #define FPEXC_DZ 0x08
  37 #define FPEXC_NV 0x10
  38
  39 #define FSR_AEXC_SHIFT 0
  40 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  41 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  42 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  43 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  44 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  45 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  46
  47 #define insn_length(x) \
  48   (((x) & 0x03) < 0x03 ? 2 : \
  49    ((x) & 0x1f) < 0x1f ? 4 : \
  50    ((x) & 0x3f) < 0x3f ? 6 : \
  51    8)
  52
  53 typedef uint64_t insn_bits_t;
  54 class insn_t
  55 {
  56 public:
  57   insn_t() = default;
  58   insn_t(insn_bits_t bits) : b(bits) {}
  59   insn_bits_t bits() { return b; }
  60   int length() { return insn_length(b); }
  61   int64_t i_imm() { return int64_t(b) >> 20; }
  62   int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
  63   int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
  64   int64_t u_imm() { return int64_t(b) >> 12 << 12; }
  65   int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
  66   uint64_t rd() { return x(7, 5); }
  67   uint64_t rs1() { return x(15, 5); }
  68   uint64_t rs2() { return x(20, 5); }
  69   uint64_t rs3() { return x(27, 5); }
  70   uint64_t rm() { return x(12, 3); }
  71   uint64_t csr() { return x(20, 12); }
  72 private:
  73   insn_bits_t b;
  74   uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
  75   uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
  76   uint64_t imm_sign() { return xs(63, 1); }
  77 };
  78
  79 template <class T, size_t N, bool zero_reg>
  80 class regfile_t
  81 {
  82 public:
  83   void reset()
  84   {
  85     memset(data, 0, sizeof(data));
  86   }
  87   void write(size_t i, T value)
  88   {
  89     if (!zero_reg || i != 0)
  90       data[i] = value;
  91   }
  92   const T& operator [] (size_t i) const
  93   {
  94     return data[i];
  95   }
  96 private:
  97   T data[N];
  98 };
  99
 100 // helpful macros, etc
 101 #define MMU (*p->get_mmu())
 102 #define STATE (*p->get_state())
 103 #define RS1 STATE.XPR[insn.rs1()]
 104 #define RS2 STATE.XPR[insn.rs2()]
 105 #define WRITE_RD(value) STATE.XPR.write(insn.rd(), value)
 106
 107 #ifdef RISCV_ENABLE_COMMITLOG
 108   #undef WRITE_RD
 109   #define WRITE_RD(value) ({ \
 110         reg_t wdata = value; /* value is a func with side-effects */ \
 111         STATE.log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
 112         STATE.XPR.write(insn.rd(), wdata); \
 113       })
 114 #endif
 115
 116 #define FRS1 STATE.FPR[insn.rs1()]
 117 #define FRS2 STATE.FPR[insn.rs2()]
 118 #define FRS3 STATE.FPR[insn.rs3()]
 119 #define WRITE_FRD(value) STATE.FPR.write(insn.rd(), value)
 120
 121 #ifdef RISCV_ENABLE_COMMITLOG
 122   #undef WRITE_FRD
 123   #define WRITE_FRD(value) ({ \
 124         freg_t wdata = value; /* value is a func with side-effects */ \
 125         STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
 126         STATE.FPR.write(insn.rd(), wdata); \
 127       })
 128 #endif
 129
 130 #define SHAMT (insn.i_imm() & 0x3F)
 131 #define BRANCH_TARGET (pc + insn.sb_imm())
 132 #define JUMP_TARGET (pc + insn.uj_imm())
 133 #define RM ({ int rm = insn.rm(); \
 134               if(rm == 7) rm = STATE.frm; \
 135               if(rm > 4) throw trap_illegal_instruction(); \
 136               rm; })
 137
 138 #define xpr64 (xlen == 64)
 139
 140 #define require_supervisor if(unlikely(!(STATE.sr & SR_S))) throw trap_privileged_instruction()
 141 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
 142 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
 143 #ifndef RISCV_ENABLE_FPU
 144 # define require_fp throw trap_illegal_instruction()
 145 #else
 146 # define require_fp if(unlikely(!(STATE.sr & SR_EF))) throw trap_fp_disabled()
 147 #endif
 148 #define require_accelerator if(unlikely(!(STATE.sr & SR_EA))) throw trap_accelerator_disabled()
 149
 150 #define cmp_trunc(reg) (reg_t(reg) << (64-xlen))
 151 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
 152                              softfloat_exceptionFlags = 0; })
 153
 154 #define sext32(x) ((sreg_t)(int32_t)(x))
 155 #define zext32(x) ((reg_t)(uint32_t)(x))
 156 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
 157 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 158
 159 #define set_pc(x) (npc = sext_xlen(x))
 160
 161 #define validate_csr(which, write) ({ \
 162   unsigned my_priv = (STATE.sr & SR_S) ? 1 : 0; \
 163   unsigned read_priv = ((which) >> 10) & 3; \
 164   unsigned write_priv = (((which) >> 8) & 3); \
 165   if (read_priv == 3) read_priv = write_priv, write_priv = -1; \
 166   if (my_priv < ((write) ? write_priv : read_priv)) \
 167     throw trap_privileged_instruction(); \
 168   (which); })
 169
 170 #endif