riscv/decode.h

   1 // See LICENSE for license details.
   2
   3 #ifndef _RISCV_DECODE_H
   4 #define _RISCV_DECODE_H
   5
   6 #if (-1 != ~0) || ((-1 >> 1) != -1)
   7 # error spike requires a two''s-complement c++ implementation
   8 #endif
   9
  10 #include <cstdint>
  11 #include <string.h>
  12 #include "encoding.h"
  13 #include "config.h"
  14 #include "common.h"
  15 #include <cinttypes>
  16
  17 typedef int64_t sreg_t;
  18 typedef uint64_t reg_t;
  19 typedef uint64_t freg_t;
  20
  21 const int NXPR = 32;
  22 const int NFPR = 32;
  23
  24 #define FP_RD_NE  0
  25 #define FP_RD_0   1
  26 #define FP_RD_DN  2
  27 #define FP_RD_UP  3
  28 #define FP_RD_NMM 4
  29
  30 #define FSR_RD_SHIFT 5
  31 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  32
  33 #define FPEXC_NX 0x01
  34 #define FPEXC_UF 0x02
  35 #define FPEXC_OF 0x04
  36 #define FPEXC_DZ 0x08
  37 #define FPEXC_NV 0x10
  38
  39 #define FSR_AEXC_SHIFT 0
  40 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  41 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  42 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  43 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  44 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  45 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  46
  47 typedef uint64_t insn_bits_t;
  48 class insn_t
  49 {
  50 public:
  51   insn_t() = default;
  52   insn_t(insn_bits_t bits) : b(bits) {}
  53   insn_bits_t bits() { return b; }
  54   int64_t i_imm() { return int64_t(b) >> 20; }
  55   int64_t s_imm() { return x(7, 5) + (xs(25, 7) << 5); }
  56   int64_t sb_imm() { return (x(8, 4) << 1) + (x(25,6) << 5) + (x(7,1) << 11) + (imm_sign() << 12); }
  57   int64_t u_imm() { return int64_t(b) >> 12 << 12; }
  58   int64_t uj_imm() { return (x(21, 10) << 1) + (x(20, 1) << 11) + (x(12, 8) << 12) + (imm_sign() << 20); }
  59   uint64_t rd() { return x(7, 5); }
  60   uint64_t rs1() { return x(15, 5); }
  61   uint64_t rs2() { return x(20, 5); }
  62   uint64_t rs3() { return x(27, 5); }
  63   uint64_t rm() { return x(12, 3); }
  64   uint64_t csr() { return x(20, 12); }
  65 private:
  66   insn_bits_t b;
  67   uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); }
  68   uint64_t xs(int lo, int len) { return int64_t(b) << (64-lo-len) >> (64-len); }
  69   uint64_t imm_sign() { return xs(63, 1); }
  70 };
  71
  72 template <class T, size_t N, bool zero_reg>
  73 class regfile_t
  74 {
  75 public:
  76   void reset()
  77   {
  78     memset(data, 0, sizeof(data));
  79   }
  80   void write(size_t i, T value)
  81   {
  82     if (!zero_reg || i != 0)
  83       data[i] = value;
  84   }
  85   const T& operator [] (size_t i) const
  86   {
  87     return data[i];
  88   }
  89 private:
  90   T data[N];
  91 };
  92
  93 // helpful macros, etc
  94 #define MMU (*p->get_mmu())
  95 #define STATE (*p->get_state())
  96 #define RS1 STATE.XPR[insn.rs1()]
  97 #define RS2 STATE.XPR[insn.rs2()]
  98 #define WRITE_RD(value) STATE.XPR.write(insn.rd(), value)
  99
 100 #ifdef RISCV_ENABLE_COMMITLOG
 101   #undef WRITE_RD
 102   #define WRITE_RD(value) ({ \
 103         reg_t wdata = value; /* value is a func with side-effects */ \
 104         STATE.log_reg_write = (commit_log_reg_t){insn.rd() << 1, wdata}; \
 105         STATE.XPR.write(insn.rd(), wdata); \
 106       })
 107 #endif
 108
 109 #define FRS1 STATE.FPR[insn.rs1()]
 110 #define FRS2 STATE.FPR[insn.rs2()]
 111 #define FRS3 STATE.FPR[insn.rs3()]
 112 #define WRITE_FRD(value) STATE.FPR.write(insn.rd(), value)
 113
 114 #ifdef RISCV_ENABLE_COMMITLOG
 115   #undef WRITE_FRD
 116   #define WRITE_FRD(value) ({ \
 117         freg_t wdata = value; /* value is a func with side-effects */ \
 118         STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \
 119         STATE.FPR.write(insn.rd(), wdata); \
 120       })
 121 #endif
 122
 123 #define SHAMT (insn.i_imm() & 0x3F)
 124 #define BRANCH_TARGET (pc + insn.sb_imm())
 125 #define JUMP_TARGET (pc + insn.uj_imm())
 126 #define RM ({ int rm = insn.rm(); \
 127               if(rm == 7) rm = STATE.frm; \
 128               if(rm > 4) throw trap_illegal_instruction(); \
 129               rm; })
 130
 131 #define xpr64 (xprlen == 64)
 132
 133 #define require_supervisor if(unlikely(!(STATE.sr & SR_S))) throw trap_privileged_instruction()
 134 #define require_xpr64 if(unlikely(!xpr64)) throw trap_illegal_instruction()
 135 #define require_xpr32 if(unlikely(xpr64)) throw trap_illegal_instruction()
 136 #ifndef RISCV_ENABLE_FPU
 137 # define require_fp throw trap_illegal_instruction()
 138 #else
 139 # define require_fp if(unlikely(!(STATE.sr & SR_EF))) throw trap_fp_disabled()
 140 #endif
 141 #define require_accelerator if(unlikely(!(STATE.sr & SR_EA))) throw trap_accelerator_disabled()
 142
 143 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 144 #define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \
 145                              softfloat_exceptionFlags = 0; })
 146
 147 #define sext32(x) ((sreg_t)(int32_t)(x))
 148 #define zext32(x) ((reg_t)(uint32_t)(x))
 149 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 150 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 151
 152 #define insn_length(x) \
 153   (((x) & 0x03) < 0x03 ? 2 : \
 154    ((x) & 0x1f) < 0x1f ? 4 : \
 155    ((x) & 0x3f) < 0x3f ? 6 : \
 156    8)
 157
 158 #define set_pc(x) (npc = sext_xprlen(x))
 159
 160 #define validate_csr(which, write) ({ \
 161   unsigned my_priv = (STATE.sr & SR_S) ? 1 : 0; \
 162   unsigned read_priv = ((which) >> 10) & 3; \
 163   unsigned write_priv = (((which) >> 8) & 3); \
 164   if (read_priv == 3) read_priv = write_priv, write_priv = -1; \
 165   if (my_priv < ((write) ? write_priv : read_priv)) \
 166     throw trap_privileged_instruction(); \
 167   (which); })
 168
 169 #endif