riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6
   7 typedef int int128_t __attribute__((mode(TI)));
   8 typedef unsigned int uint128_t __attribute__((mode(TI)));
   9
  10 typedef int64_t sreg_t;
  11 typedef uint64_t reg_t;
  12 typedef uint64_t freg_t;
  13
  14 const int OPCODE_BITS = 7;
  15
  16 const int XPRID_BITS = 5;
  17 const int NXPR = 1 << XPRID_BITS;
  18
  19 const int FPR_BITS = 64;
  20 const int FPRID_BITS = 5;
  21 const int NFPR = 1 << FPRID_BITS;
  22
  23 const int IMM_BITS = 12;
  24 const int IMMLO_BITS = 7;
  25 const int TARGET_BITS = 25;
  26 const int FUNCT_BITS = 3;
  27 const int FUNCTR_BITS = 7;
  28 const int FFUNCT_BITS = 2;
  29 const int RM_BITS = 3;
  30 const int BIGIMM_BITS = 20;
  31 const int BRANCH_ALIGN_BITS = 1;
  32 const int JUMP_ALIGN_BITS = 1;
  33
  34 #define SR_ET    0x0000000000000001ULL
  35 #define SR_EF    0x0000000000000002ULL
  36 #define SR_EV    0x0000000000000004ULL
  37 #define SR_EC    0x0000000000000008ULL
  38 #define SR_PS    0x0000000000000010ULL
  39 #define SR_S     0x0000000000000020ULL
  40 #define SR_UX    0x0000000000000040ULL
  41 #define SR_SX    0x0000000000000080ULL
  42 #define SR_IM    0x000000000000FF00ULL
  43 #define SR_VM    0x0000000000010000ULL
  44 #define SR_ZERO  ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_UX|SR_SX|SR_IM|SR_VM)
  45 #define SR_IM_SHIFT 8
  46 #define IPI_IRQ 5
  47 #define TIMER_IRQ 7
  48
  49 #define FP_RD_NE  0
  50 #define FP_RD_0   1
  51 #define FP_RD_DN  2
  52 #define FP_RD_UP  3
  53 #define FP_RD_NMM 4
  54
  55 #define FSR_RD_SHIFT 5
  56 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  57
  58 #define FPEXC_NX 0x01
  59 #define FPEXC_UF 0x02
  60 #define FPEXC_OF 0x04
  61 #define FPEXC_DZ 0x08
  62 #define FPEXC_NV 0x10
  63
  64 #define FSR_AEXC_SHIFT 0
  65 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  66 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  67 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  68 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  69 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  70 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  71
  72 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  73
  74 // note: bit fields are in little-endian order
  75 struct itype_t
  76 {
  77   unsigned opcode : OPCODE_BITS;
  78   unsigned funct : FUNCT_BITS;
  79   signed imm12 : IMM_BITS;
  80   unsigned rs1 : XPRID_BITS;
  81   unsigned rd : XPRID_BITS;
  82 };
  83
  84 struct btype_t
  85 {
  86   unsigned opcode : OPCODE_BITS;
  87   unsigned funct : FUNCT_BITS;
  88   unsigned immlo : IMMLO_BITS;
  89   unsigned rs2 : XPRID_BITS;
  90   unsigned rs1 : XPRID_BITS;
  91   signed immhi : IMM_BITS-IMMLO_BITS;
  92 };
  93
  94 struct jtype_t
  95 {
  96   unsigned jump_opcode : OPCODE_BITS;
  97   signed target : TARGET_BITS;
  98 };
  99
 100 struct rtype_t
 101 {
 102   unsigned opcode : OPCODE_BITS;
 103   unsigned funct : FUNCT_BITS;
 104   unsigned functr : FUNCTR_BITS;
 105   unsigned rs2 : XPRID_BITS;
 106   unsigned rs1 : XPRID_BITS;
 107   unsigned rd : XPRID_BITS;
 108 };
 109
 110 struct ltype_t
 111 {
 112   unsigned opcode : OPCODE_BITS;
 113   unsigned bigimm : BIGIMM_BITS;
 114   unsigned rd : XPRID_BITS;
 115 };
 116
 117 struct ftype_t
 118 {
 119   unsigned opcode : OPCODE_BITS;
 120   unsigned ffunct : FFUNCT_BITS;
 121   unsigned rm : RM_BITS;
 122   unsigned rs3 : FPRID_BITS;
 123   unsigned rs2 : FPRID_BITS;
 124   unsigned rs1 : FPRID_BITS;
 125   unsigned rd  : FPRID_BITS;
 126 };
 127
 128 union insn_t
 129 {
 130   itype_t itype;
 131   jtype_t jtype;
 132   rtype_t rtype;
 133   btype_t btype;
 134   ltype_t ltype;
 135   ftype_t ftype;
 136   uint32_t bits;
 137 };
 138
 139 #include <stdio.h>
 140 class do_writeback
 141 {
 142 public:
 143   do_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 144
 145   const do_writeback& operator = (reg_t rhs)
 146   {
 147 #if 0
 148     printf("R[%x] <= %llx\n",rd,(long long)rhs);
 149 #endif
 150     rf[rd] = rhs;
 151     rf[0] = 0;
 152     return *this;
 153   }
 154
 155   operator reg_t() { return rf[rd]; }
 156
 157 private:
 158   reg_t* rf;
 159   int rd;
 160 };
 161
 162 #define throw_illegal_instruction \
 163   ({ if (utmode) throw trap_vector_illegal_instruction; \
 164      else throw trap_illegal_instruction; })
 165
 166 // helpful macros, etc
 167 #define RS1 XPR[insn.rtype.rs1]
 168 #define RS2 XPR[insn.rtype.rs2]
 169 #define RD do_writeback(XPR,insn.rtype.rd)
 170 #define RA do_writeback(XPR,1)
 171 #define FRS1 FPR[insn.ftype.rs1]
 172 #define FRS2 FPR[insn.ftype.rs2]
 173 #define FRS3 FPR[insn.ftype.rs3]
 174 #define FRD FPR[insn.ftype.rd]
 175 #define BIGIMM insn.ltype.bigimm
 176 #define SIMM insn.itype.imm12
 177 #define BIMM ((signed)insn.btype.immlo | (insn.btype.immhi << IMMLO_BITS))
 178 #define SHAMT (insn.itype.imm12 & 0x3F)
 179 #define SHAMTW (insn.itype.imm12 & 0x1F)
 180 #define TARGET insn.jtype.target
 181 #define BRANCH_TARGET (pc + (BIMM << BRANCH_ALIGN_BITS))
 182 #define JUMP_TARGET (pc + (TARGET << JUMP_ALIGN_BITS))
 183 #define RM ({ int rm = insn.ftype.rm; \
 184               if(rm == 7) rm = (fsr & FSR_RD) >> FSR_RD_SHIFT; \
 185               if(rm > 4) throw_illegal_instruction; \
 186               rm; })
 187
 188 #define require_supervisor if(unlikely(!(sr & SR_S))) throw trap_privileged_instruction
 189 #define xpr64 (xprlen == 64)
 190 #define require_xpr64 if(unlikely(!xpr64)) throw_illegal_instruction
 191 #define require_xpr32 if(unlikely(xpr64)) throw_illegal_instruction
 192 #define require_fp if(unlikely(!(sr & SR_EF))) throw trap_fp_disabled
 193 #define require_vector \
 194   ({ if(!(sr & SR_EV)) throw trap_vector_disabled; \
 195     else if (!utmode && (vecbanks_count < 3)) throw trap_vector_bank; \
 196   })
 197 #define cmp_trunc(reg) (reg_t(reg) << (64-xprlen))
 198 #define set_fp_exceptions ({ set_fsr(fsr | \
 199                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 200                              softfloat_exceptionFlags = 0; })
 201
 202 #define sext32(x) ((sreg_t)(int32_t)(x))
 203 #define zext32(x) ((reg_t)(uint32_t)(x))
 204 #define sext_xprlen(x) (((sreg_t)(x) << (64-xprlen)) >> (64-xprlen))
 205 #define zext_xprlen(x) (((reg_t)(x) << (64-xprlen)) >> (64-xprlen))
 206
 207 // RVC stuff
 208
 209 #define INSN_IS_RVC(x) (((x) & 0x3) < 0x3)
 210 #define insn_length(x) (INSN_IS_RVC(x) ? 2 : 4)
 211 #define require_rvc if(!(sr & SR_EC)) throw_illegal_instruction
 212
 213 #define CRD_REGNUM ((insn.bits >> 5) & 0x1f)
 214 #define CRD do_writeback(XPR, CRD_REGNUM)
 215 #define CRS1 XPR[(insn.bits >> 10) & 0x1f]
 216 #define CRS2 XPR[(insn.bits >> 5) & 0x1f]
 217 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
 218 #define CIMM5U ((insn.bits >> 5) & 0x1f)
 219 #define CIMM5 ((int32_t)CIMM5U << 27 >> 27)
 220 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
 221 #define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
 222 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
 223
 224 static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
 225 #define rvc_rd_regmap rvc_rs1_regmap
 226 #define rvc_rs2b_regmap rvc_rs1_regmap
 227 static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
 228 #define CRDS XPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
 229 #define FCRDS FPR[rvc_rd_regmap[(insn.bits >> 13) & 0x7]]
 230 #define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
 231 #define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 232 #define CRS2BS XPR[rvc_rs2b_regmap[(insn.bits >> 5) & 0x7]]
 233 #define FCRS2S FPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 234
 235 // vector stuff
 236 #define VL vl
 237
 238 #define UT_RS1(idx) uts[idx]->XPR[insn.rtype.rs1]
 239 #define UT_RS2(idx) uts[idx]->XPR[insn.rtype.rs2]
 240 #define UT_RD(idx) do_writeback(uts[idx]->XPR,insn.rtype.rd)
 241 #define UT_RA(idx) do_writeback(uts[idx]->XPR,1)
 242 #define UT_FRS1(idx) uts[idx]->FPR[insn.ftype.rs1]
 243 #define UT_FRS2(idx) uts[idx]->FPR[insn.ftype.rs2]
 244 #define UT_FRS3(idx) uts[idx]->FPR[insn.ftype.rs3]
 245 #define UT_FRD(idx) uts[idx]->FPR[insn.ftype.rd]
 246 #define UT_RM(idx) ((insn.ftype.rm != 7) ? insn.ftype.rm : \
 247               ((uts[idx]->fsr & FSR_RD) >> FSR_RD_SHIFT))
 248
 249 #define UT_LOOP_START for (int i=0;i<VL; i++) {
 250 #define UT_LOOP_END }
 251 #define UT_LOOP_RS1 UT_RS1(i)
 252 #define UT_LOOP_RS2 UT_RS2(i)
 253 #define UT_LOOP_RD UT_RD(i)
 254 #define UT_LOOP_RA UT_RA(i)
 255 #define UT_LOOP_FRS1 UT_FRS1(i)
 256 #define UT_LOOP_FRS2 UT_FRS2(i)
 257 #define UT_LOOP_FRS3 UT_FRS3(i)
 258 #define UT_LOOP_FRD UT_FRD(i)
 259 #define UT_LOOP_RM UT_RM(i)
 260
 261 #define VEC_LOAD(dst, func, inc) \
 262   reg_t addr = RS1; \
 263   UT_LOOP_START \
 264     UT_LOOP_##dst = mmu.func(addr); \
 265     addr += inc; \
 266   UT_LOOP_END
 267
 268 #define VEC_STORE(src, func, inc) \
 269   reg_t addr = RS1; \
 270   UT_LOOP_START \
 271     mmu.func(addr, UT_LOOP_##src); \
 272     addr += inc; \
 273   UT_LOOP_END
 274
 275 enum vt_command_t
 276 {
 277   vt_command_stop,
 278 };
 279
 280 #endif