riscv/encoding.h

   1 // See LICENSE for license details.
   2
   3 #ifndef RISCV_CSR_ENCODING_H
   4 #define RISCV_CSR_ENCODING_H
   5
   6 #define MSTATUS_UIE         0x00000001
   7 #define MSTATUS_SIE         0x00000002
   8 #define MSTATUS_HIE         0x00000004
   9 #define MSTATUS_MIE         0x00000008
  10 #define MSTATUS_UPIE        0x00000010
  11 #define MSTATUS_SPIE        0x00000020
  12 #define MSTATUS_HPIE        0x00000040
  13 #define MSTATUS_MPIE        0x00000080
  14 #define MSTATUS_SPP         0x00000100
  15 #define MSTATUS_HPP         0x00000600
  16 #define MSTATUS_MPP         0x00001800
  17 #define MSTATUS_FS          0x00006000
  18 #define MSTATUS_XS          0x00018000
  19 #define MSTATUS_MPRV        0x00020000
  20 #define MSTATUS_VM          0x007C0000
  21 #define MSTATUS32_SD        0x80000000
  22 #define MSTATUS64_SD        0x8000000000000000
  23
  24 #define SSTATUS_UIE         0x00000001
  25 #define SSTATUS_SIE         0x00000002
  26 #define SSTATUS_UPIE        0x00000010
  27 #define SSTATUS_SPIE        0x00000020
  28 #define SSTATUS_SPP         0x00000100
  29 #define SSTATUS_FS          0x00006000
  30 #define SSTATUS_XS          0x00018000
  31 #define SSTATUS_VM          0x007C0000
  32 #define SSTATUS32_SD        0x80000000
  33 #define SSTATUS64_SD        0x8000000000000000
  34
  35 #define MIP_SSIP            (1 << IRQ_S_SOFT)
  36 #define MIP_HSIP            (1 << IRQ_H_SOFT)
  37 #define MIP_MSIP            (1 << IRQ_M_SOFT)
  38 #define MIP_STIP            (1 << IRQ_S_TIMER)
  39 #define MIP_HTIP            (1 << IRQ_H_TIMER)
  40 #define MIP_MTIP            (1 << IRQ_M_TIMER)
  41
  42 #define SIP_SSIP MIP_SSIP
  43 #define SIP_STIP MIP_STIP
  44
  45 #define PRV_U 0
  46 #define PRV_S 1
  47 #define PRV_H 2
  48 #define PRV_M 3
  49
  50 #define VM_MBARE 0
  51 #define VM_MBB   1
  52 #define VM_MBBID 2
  53 #define VM_SV32  8
  54 #define VM_SV39  9
  55 #define VM_SV48  10
  56
  57 #define IRQ_S_SOFT   1
  58 #define IRQ_H_SOFT   2
  59 #define IRQ_M_SOFT   3
  60 #define IRQ_S_TIMER  5
  61 #define IRQ_H_TIMER  6
  62 #define IRQ_M_TIMER  7
  63 #define IRQ_COP      8
  64 #define IRQ_HOST     9
  65
  66 #define IMPL_ROCKET 1
  67
  68 #define DEFAULT_MTVEC 0x100
  69
  70 // page table entry (PTE) fields
  71 #define PTE_V     0x001 // Valid
  72 #define PTE_TYPE  0x01E // Type
  73 #define PTE_R     0x020 // Referenced
  74 #define PTE_D     0x040 // Dirty
  75 #define PTE_SOFT  0x380 // Reserved for Software
  76
  77 #define PTE_TYPE_TABLE        0x00
  78 #define PTE_TYPE_TABLE_GLOBAL 0x02
  79 #define PTE_TYPE_URX_SR       0x04
  80 #define PTE_TYPE_URWX_SRW     0x06
  81 #define PTE_TYPE_UR_SR        0x08
  82 #define PTE_TYPE_URW_SRW      0x0A
  83 #define PTE_TYPE_URX_SRX      0x0C
  84 #define PTE_TYPE_URWX_SRWX    0x0E
  85 #define PTE_TYPE_SR           0x10
  86 #define PTE_TYPE_SRW          0x12
  87 #define PTE_TYPE_SRX          0x14
  88 #define PTE_TYPE_SRWX         0x16
  89 #define PTE_TYPE_SR_GLOBAL    0x18
  90 #define PTE_TYPE_SRW_GLOBAL   0x1A
  91 #define PTE_TYPE_SRX_GLOBAL   0x1C
  92 #define PTE_TYPE_SRWX_GLOBAL  0x1E
  93
  94 #define PTE_PPN_SHIFT 10
  95
  96 #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
  97 #define PTE_UR(PTE)    ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
  98 #define PTE_UW(PTE)    ((0x00008880U >> ((PTE) & 0x1F)) & 1)
  99 #define PTE_UX(PTE)    ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
 100 #define PTE_SR(PTE)    ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
 101 #define PTE_SW(PTE)    ((0x88888880U >> ((PTE) & 0x1F)) & 1)
 102 #define PTE_SX(PTE)    ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
 103
 104 #define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \
 105   ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
 106    (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
 107              ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
 108
 109 #ifdef __riscv
 110
 111 #ifdef __riscv64
 112 # define MSTATUS_SD MSTATUS64_SD
 113 # define SSTATUS_SD SSTATUS64_SD
 114 # define RISCV_PGLEVEL_BITS 9
 115 #else
 116 # define MSTATUS_SD MSTATUS32_SD
 117 # define SSTATUS_SD SSTATUS32_SD
 118 # define RISCV_PGLEVEL_BITS 10
 119 #endif
 120 #define RISCV_PGSHIFT 12
 121 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
 122
 123 #ifndef __ASSEMBLER__
 124
 125 #ifdef __GNUC__
 126
 127 #define read_csr(reg) ({ unsigned long __tmp; \
 128   asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
 129   __tmp; })
 130
 131 #define write_csr(reg, val) \
 132   asm volatile ("csrw " #reg ", %0" :: "r"(val))
 133
 134 #define swap_csr(reg, val) ({ long __tmp; \
 135   asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
 136   __tmp; })
 137
 138 #define set_csr(reg, bit) ({ unsigned long __tmp; \
 139   if (__builtin_constant_p(bit) && (bit) < 32) \
 140     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 141   else \
 142     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
 143   __tmp; })
 144
 145 #define clear_csr(reg, bit) ({ unsigned long __tmp; \
 146   if (__builtin_constant_p(bit) && (bit) < 32) \
 147     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 148   else \
 149     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
 150   __tmp; })
 151
 152 #define rdtime() read_csr(time)
 153 #define rdcycle() read_csr(cycle)
 154 #define rdinstret() read_csr(instret)
 155
 156 #endif
 157
 158 #endif
 159
 160 #endif
 161
 162 #endif
 163 /* Automatically generated by parse-opcodes */
 164 #ifndef RISCV_ENCODING_H
 165 #define RISCV_ENCODING_H
 166 #define MATCH_BEQ 0x63
 167 #define MASK_BEQ  0x707f
 168 #define MATCH_BNE 0x1063
 169 #define MASK_BNE  0x707f
 170 #define MATCH_BLT 0x4063
 171 #define MASK_BLT  0x707f
 172 #define MATCH_BGE 0x5063
 173 #define MASK_BGE  0x707f
 174 #define MATCH_BLTU 0x6063
 175 #define MASK_BLTU  0x707f
 176 #define MATCH_BGEU 0x7063
 177 #define MASK_BGEU  0x707f
 178 #define MATCH_JALR 0x67
 179 #define MASK_JALR  0x707f
 180 #define MATCH_JAL 0x6f
 181 #define MASK_JAL  0x7f
 182 #define MATCH_LUI 0x37
 183 #define MASK_LUI  0x7f
 184 #define MATCH_AUIPC 0x17
 185 #define MASK_AUIPC  0x7f
 186 #define MATCH_ADDI 0x13
 187 #define MASK_ADDI  0x707f
 188 #define MATCH_SLLI 0x1013
 189 #define MASK_SLLI  0xfc00707f
 190 #define MATCH_SLTI 0x2013
 191 #define MASK_SLTI  0x707f
 192 #define MATCH_SLTIU 0x3013
 193 #define MASK_SLTIU  0x707f
 194 #define MATCH_XORI 0x4013
 195 #define MASK_XORI  0x707f
 196 #define MATCH_SRLI 0x5013
 197 #define MASK_SRLI  0xfc00707f
 198 #define MATCH_SRAI 0x40005013
 199 #define MASK_SRAI  0xfc00707f
 200 #define MATCH_ORI 0x6013
 201 #define MASK_ORI  0x707f
 202 #define MATCH_ANDI 0x7013
 203 #define MASK_ANDI  0x707f
 204 #define MATCH_ADD 0x33
 205 #define MASK_ADD  0xfe00707f
 206 #define MATCH_SUB 0x40000033
 207 #define MASK_SUB  0xfe00707f
 208 #define MATCH_SLL 0x1033
 209 #define MASK_SLL  0xfe00707f
 210 #define MATCH_SLT 0x2033
 211 #define MASK_SLT  0xfe00707f
 212 #define MATCH_SLTU 0x3033
 213 #define MASK_SLTU  0xfe00707f
 214 #define MATCH_XOR 0x4033
 215 #define MASK_XOR  0xfe00707f
 216 #define MATCH_SRL 0x5033
 217 #define MASK_SRL  0xfe00707f
 218 #define MATCH_SRA 0x40005033
 219 #define MASK_SRA  0xfe00707f
 220 #define MATCH_OR 0x6033
 221 #define MASK_OR  0xfe00707f
 222 #define MATCH_AND 0x7033
 223 #define MASK_AND  0xfe00707f
 224 #define MATCH_ADDIW 0x1b
 225 #define MASK_ADDIW  0x707f
 226 #define MATCH_SLLIW 0x101b
 227 #define MASK_SLLIW  0xfe00707f
 228 #define MATCH_SRLIW 0x501b
 229 #define MASK_SRLIW  0xfe00707f
 230 #define MATCH_SRAIW 0x4000501b
 231 #define MASK_SRAIW  0xfe00707f
 232 #define MATCH_ADDW 0x3b
 233 #define MASK_ADDW  0xfe00707f
 234 #define MATCH_SUBW 0x4000003b
 235 #define MASK_SUBW  0xfe00707f
 236 #define MATCH_SLLW 0x103b
 237 #define MASK_SLLW  0xfe00707f
 238 #define MATCH_SRLW 0x503b
 239 #define MASK_SRLW  0xfe00707f
 240 #define MATCH_SRAW 0x4000503b
 241 #define MASK_SRAW  0xfe00707f
 242 #define MATCH_LB 0x3
 243 #define MASK_LB  0x707f
 244 #define MATCH_LH 0x1003
 245 #define MASK_LH  0x707f
 246 #define MATCH_LW 0x2003
 247 #define MASK_LW  0x707f
 248 #define MATCH_LD 0x3003
 249 #define MASK_LD  0x707f
 250 #define MATCH_LBU 0x4003
 251 #define MASK_LBU  0x707f
 252 #define MATCH_LHU 0x5003
 253 #define MASK_LHU  0x707f
 254 #define MATCH_LWU 0x6003
 255 #define MASK_LWU  0x707f
 256 #define MATCH_SB 0x23
 257 #define MASK_SB  0x707f
 258 #define MATCH_SH 0x1023
 259 #define MASK_SH  0x707f
 260 #define MATCH_SW 0x2023
 261 #define MASK_SW  0x707f
 262 #define MATCH_SD 0x3023
 263 #define MASK_SD  0x707f
 264 #define MATCH_FENCE 0xf
 265 #define MASK_FENCE  0x707f
 266 #define MATCH_FENCE_I 0x100f
 267 #define MASK_FENCE_I  0x707f
 268 #define MATCH_MUL 0x2000033
 269 #define MASK_MUL  0xfe00707f
 270 #define MATCH_MULH 0x2001033
 271 #define MASK_MULH  0xfe00707f
 272 #define MATCH_MULHSU 0x2002033
 273 #define MASK_MULHSU  0xfe00707f
 274 #define MATCH_MULHU 0x2003033
 275 #define MASK_MULHU  0xfe00707f
 276 #define MATCH_DIV 0x2004033
 277 #define MASK_DIV  0xfe00707f
 278 #define MATCH_DIVU 0x2005033
 279 #define MASK_DIVU  0xfe00707f
 280 #define MATCH_REM 0x2006033
 281 #define MASK_REM  0xfe00707f
 282 #define MATCH_REMU 0x2007033
 283 #define MASK_REMU  0xfe00707f
 284 #define MATCH_MULW 0x200003b
 285 #define MASK_MULW  0xfe00707f
 286 #define MATCH_DIVW 0x200403b
 287 #define MASK_DIVW  0xfe00707f
 288 #define MATCH_DIVUW 0x200503b
 289 #define MASK_DIVUW  0xfe00707f
 290 #define MATCH_REMW 0x200603b
 291 #define MASK_REMW  0xfe00707f
 292 #define MATCH_REMUW 0x200703b
 293 #define MASK_REMUW  0xfe00707f
 294 #define MATCH_AMOADD_W 0x202f
 295 #define MASK_AMOADD_W  0xf800707f
 296 #define MATCH_AMOXOR_W 0x2000202f
 297 #define MASK_AMOXOR_W  0xf800707f
 298 #define MATCH_AMOOR_W 0x4000202f
 299 #define MASK_AMOOR_W  0xf800707f
 300 #define MATCH_AMOAND_W 0x6000202f
 301 #define MASK_AMOAND_W  0xf800707f
 302 #define MATCH_AMOMIN_W 0x8000202f
 303 #define MASK_AMOMIN_W  0xf800707f
 304 #define MATCH_AMOMAX_W 0xa000202f
 305 #define MASK_AMOMAX_W  0xf800707f
 306 #define MATCH_AMOMINU_W 0xc000202f
 307 #define MASK_AMOMINU_W  0xf800707f
 308 #define MATCH_AMOMAXU_W 0xe000202f
 309 #define MASK_AMOMAXU_W  0xf800707f
 310 #define MATCH_AMOSWAP_W 0x800202f
 311 #define MASK_AMOSWAP_W  0xf800707f
 312 #define MATCH_LR_W 0x1000202f
 313 #define MASK_LR_W  0xf9f0707f
 314 #define MATCH_SC_W 0x1800202f
 315 #define MASK_SC_W  0xf800707f
 316 #define MATCH_AMOADD_D 0x302f
 317 #define MASK_AMOADD_D  0xf800707f
 318 #define MATCH_AMOXOR_D 0x2000302f
 319 #define MASK_AMOXOR_D  0xf800707f
 320 #define MATCH_AMOOR_D 0x4000302f
 321 #define MASK_AMOOR_D  0xf800707f
 322 #define MATCH_AMOAND_D 0x6000302f
 323 #define MASK_AMOAND_D  0xf800707f
 324 #define MATCH_AMOMIN_D 0x8000302f
 325 #define MASK_AMOMIN_D  0xf800707f
 326 #define MATCH_AMOMAX_D 0xa000302f
 327 #define MASK_AMOMAX_D  0xf800707f
 328 #define MATCH_AMOMINU_D 0xc000302f
 329 #define MASK_AMOMINU_D  0xf800707f
 330 #define MATCH_AMOMAXU_D 0xe000302f
 331 #define MASK_AMOMAXU_D  0xf800707f
 332 #define MATCH_AMOSWAP_D 0x800302f
 333 #define MASK_AMOSWAP_D  0xf800707f
 334 #define MATCH_LR_D 0x1000302f
 335 #define MASK_LR_D  0xf9f0707f
 336 #define MATCH_SC_D 0x1800302f
 337 #define MASK_SC_D  0xf800707f
 338 #define MATCH_SCALL 0x73
 339 #define MASK_SCALL  0xffffffff
 340 #define MATCH_SBREAK 0x100073
 341 #define MASK_SBREAK  0xffffffff
 342 #define MATCH_SRET 0x10200073
 343 #define MASK_SRET  0xffffffff
 344 #define MATCH_SFENCE_VM 0x10400073
 345 #define MASK_SFENCE_VM  0xfff07fff
 346 #define MATCH_WFI 0x10500073
 347 #define MASK_WFI  0xffffffff
 348 #define MATCH_CSRRW 0x1073
 349 #define MASK_CSRRW  0x707f
 350 #define MATCH_CSRRS 0x2073
 351 #define MASK_CSRRS  0x707f
 352 #define MATCH_CSRRC 0x3073
 353 #define MASK_CSRRC  0x707f
 354 #define MATCH_CSRRWI 0x5073
 355 #define MASK_CSRRWI  0x707f
 356 #define MATCH_CSRRSI 0x6073
 357 #define MASK_CSRRSI  0x707f
 358 #define MATCH_CSRRCI 0x7073
 359 #define MASK_CSRRCI  0x707f
 360 #define MATCH_FADD_S 0x53
 361 #define MASK_FADD_S  0xfe00007f
 362 #define MATCH_FSUB_S 0x8000053
 363 #define MASK_FSUB_S  0xfe00007f
 364 #define MATCH_FMUL_S 0x10000053
 365 #define MASK_FMUL_S  0xfe00007f
 366 #define MATCH_FDIV_S 0x18000053
 367 #define MASK_FDIV_S  0xfe00007f
 368 #define MATCH_FSGNJ_S 0x20000053
 369 #define MASK_FSGNJ_S  0xfe00707f
 370 #define MATCH_FSGNJN_S 0x20001053
 371 #define MASK_FSGNJN_S  0xfe00707f
 372 #define MATCH_FSGNJX_S 0x20002053
 373 #define MASK_FSGNJX_S  0xfe00707f
 374 #define MATCH_FMIN_S 0x28000053
 375 #define MASK_FMIN_S  0xfe00707f
 376 #define MATCH_FMAX_S 0x28001053
 377 #define MASK_FMAX_S  0xfe00707f
 378 #define MATCH_FSQRT_S 0x58000053
 379 #define MASK_FSQRT_S  0xfff0007f
 380 #define MATCH_FADD_D 0x2000053
 381 #define MASK_FADD_D  0xfe00007f
 382 #define MATCH_FSUB_D 0xa000053
 383 #define MASK_FSUB_D  0xfe00007f
 384 #define MATCH_FMUL_D 0x12000053
 385 #define MASK_FMUL_D  0xfe00007f
 386 #define MATCH_FDIV_D 0x1a000053
 387 #define MASK_FDIV_D  0xfe00007f
 388 #define MATCH_FSGNJ_D 0x22000053
 389 #define MASK_FSGNJ_D  0xfe00707f
 390 #define MATCH_FSGNJN_D 0x22001053
 391 #define MASK_FSGNJN_D  0xfe00707f
 392 #define MATCH_FSGNJX_D 0x22002053
 393 #define MASK_FSGNJX_D  0xfe00707f
 394 #define MATCH_FMIN_D 0x2a000053
 395 #define MASK_FMIN_D  0xfe00707f
 396 #define MATCH_FMAX_D 0x2a001053
 397 #define MASK_FMAX_D  0xfe00707f
 398 #define MATCH_FCVT_S_D 0x40100053
 399 #define MASK_FCVT_S_D  0xfff0007f
 400 #define MATCH_FCVT_D_S 0x42000053
 401 #define MASK_FCVT_D_S  0xfff0007f
 402 #define MATCH_FSQRT_D 0x5a000053
 403 #define MASK_FSQRT_D  0xfff0007f
 404 #define MATCH_FLE_S 0xa0000053
 405 #define MASK_FLE_S  0xfe00707f
 406 #define MATCH_FLT_S 0xa0001053
 407 #define MASK_FLT_S  0xfe00707f
 408 #define MATCH_FEQ_S 0xa0002053
 409 #define MASK_FEQ_S  0xfe00707f
 410 #define MATCH_FLE_D 0xa2000053
 411 #define MASK_FLE_D  0xfe00707f
 412 #define MATCH_FLT_D 0xa2001053
 413 #define MASK_FLT_D  0xfe00707f
 414 #define MATCH_FEQ_D 0xa2002053
 415 #define MASK_FEQ_D  0xfe00707f
 416 #define MATCH_FCVT_W_S 0xc0000053
 417 #define MASK_FCVT_W_S  0xfff0007f
 418 #define MATCH_FCVT_WU_S 0xc0100053
 419 #define MASK_FCVT_WU_S  0xfff0007f
 420 #define MATCH_FCVT_L_S 0xc0200053
 421 #define MASK_FCVT_L_S  0xfff0007f
 422 #define MATCH_FCVT_LU_S 0xc0300053
 423 #define MASK_FCVT_LU_S  0xfff0007f
 424 #define MATCH_FMV_X_S 0xe0000053
 425 #define MASK_FMV_X_S  0xfff0707f
 426 #define MATCH_FCLASS_S 0xe0001053
 427 #define MASK_FCLASS_S  0xfff0707f
 428 #define MATCH_FCVT_W_D 0xc2000053
 429 #define MASK_FCVT_W_D  0xfff0007f
 430 #define MATCH_FCVT_WU_D 0xc2100053
 431 #define MASK_FCVT_WU_D  0xfff0007f
 432 #define MATCH_FCVT_L_D 0xc2200053
 433 #define MASK_FCVT_L_D  0xfff0007f
 434 #define MATCH_FCVT_LU_D 0xc2300053
 435 #define MASK_FCVT_LU_D  0xfff0007f
 436 #define MATCH_FMV_X_D 0xe2000053
 437 #define MASK_FMV_X_D  0xfff0707f
 438 #define MATCH_FCLASS_D 0xe2001053
 439 #define MASK_FCLASS_D  0xfff0707f
 440 #define MATCH_FCVT_S_W 0xd0000053
 441 #define MASK_FCVT_S_W  0xfff0007f
 442 #define MATCH_FCVT_S_WU 0xd0100053
 443 #define MASK_FCVT_S_WU  0xfff0007f
 444 #define MATCH_FCVT_S_L 0xd0200053
 445 #define MASK_FCVT_S_L  0xfff0007f
 446 #define MATCH_FCVT_S_LU 0xd0300053
 447 #define MASK_FCVT_S_LU  0xfff0007f
 448 #define MATCH_FMV_S_X 0xf0000053
 449 #define MASK_FMV_S_X  0xfff0707f
 450 #define MATCH_FCVT_D_W 0xd2000053
 451 #define MASK_FCVT_D_W  0xfff0007f
 452 #define MATCH_FCVT_D_WU 0xd2100053
 453 #define MASK_FCVT_D_WU  0xfff0007f
 454 #define MATCH_FCVT_D_L 0xd2200053
 455 #define MASK_FCVT_D_L  0xfff0007f
 456 #define MATCH_FCVT_D_LU 0xd2300053
 457 #define MASK_FCVT_D_LU  0xfff0007f
 458 #define MATCH_FMV_D_X 0xf2000053
 459 #define MASK_FMV_D_X  0xfff0707f
 460 #define MATCH_FLW 0x2007
 461 #define MASK_FLW  0x707f
 462 #define MATCH_FLD 0x3007
 463 #define MASK_FLD  0x707f
 464 #define MATCH_FSW 0x2027
 465 #define MASK_FSW  0x707f
 466 #define MATCH_FSD 0x3027
 467 #define MASK_FSD  0x707f
 468 #define MATCH_FMADD_S 0x43
 469 #define MASK_FMADD_S  0x600007f
 470 #define MATCH_FMSUB_S 0x47
 471 #define MASK_FMSUB_S  0x600007f
 472 #define MATCH_FNMSUB_S 0x4b
 473 #define MASK_FNMSUB_S  0x600007f
 474 #define MATCH_FNMADD_S 0x4f
 475 #define MASK_FNMADD_S  0x600007f
 476 #define MATCH_FMADD_D 0x2000043
 477 #define MASK_FMADD_D  0x600007f
 478 #define MATCH_FMSUB_D 0x2000047
 479 #define MASK_FMSUB_D  0x600007f
 480 #define MATCH_FNMSUB_D 0x200004b
 481 #define MASK_FNMSUB_D  0x600007f
 482 #define MATCH_FNMADD_D 0x200004f
 483 #define MASK_FNMADD_D  0x600007f
 484 #define MATCH_C_NOP 0x1
 485 #define MASK_C_NOP  0xffff
 486 #define MATCH_C_ADDI16SP 0x6101
 487 #define MASK_C_ADDI16SP  0xef83
 488 #define MATCH_C_JR 0x8002
 489 #define MASK_C_JR  0xf07f
 490 #define MATCH_C_JALR 0x9002
 491 #define MASK_C_JALR  0xf07f
 492 #define MATCH_C_EBREAK 0x9002
 493 #define MASK_C_EBREAK  0xffff
 494 #define MATCH_C_LD 0x6000
 495 #define MASK_C_LD  0xe003
 496 #define MATCH_C_SD 0xe000
 497 #define MASK_C_SD  0xe003
 498 #define MATCH_C_ADDIW 0x2001
 499 #define MASK_C_ADDIW  0xe003
 500 #define MATCH_C_LDSP 0x6002
 501 #define MASK_C_LDSP  0xe003
 502 #define MATCH_C_SDSP 0xe002
 503 #define MASK_C_SDSP  0xe003
 504 #define MATCH_C_ADDI4SPN 0x0
 505 #define MASK_C_ADDI4SPN  0xe003
 506 #define MATCH_C_FLD 0x2000
 507 #define MASK_C_FLD  0xe003
 508 #define MATCH_C_LW 0x4000
 509 #define MASK_C_LW  0xe003
 510 #define MATCH_C_FLW 0x6000
 511 #define MASK_C_FLW  0xe003
 512 #define MATCH_C_FSD 0xa000
 513 #define MASK_C_FSD  0xe003
 514 #define MATCH_C_SW 0xc000
 515 #define MASK_C_SW  0xe003
 516 #define MATCH_C_FSW 0xe000
 517 #define MASK_C_FSW  0xe003
 518 #define MATCH_C_ADDI 0x1
 519 #define MASK_C_ADDI  0xe003
 520 #define MATCH_C_JAL 0x2001
 521 #define MASK_C_JAL  0xe003
 522 #define MATCH_C_LI 0x4001
 523 #define MASK_C_LI  0xe003
 524 #define MATCH_C_LUI 0x6001
 525 #define MASK_C_LUI  0xe003
 526 #define MATCH_C_SRLI 0x8001
 527 #define MASK_C_SRLI  0xec03
 528 #define MATCH_C_SRAI 0x8401
 529 #define MASK_C_SRAI  0xec03
 530 #define MATCH_C_ANDI 0x8801
 531 #define MASK_C_ANDI  0xec03
 532 #define MATCH_C_SUB 0x8c01
 533 #define MASK_C_SUB  0xfc63
 534 #define MATCH_C_XOR 0x8c21
 535 #define MASK_C_XOR  0xfc63
 536 #define MATCH_C_OR 0x8c41
 537 #define MASK_C_OR  0xfc63
 538 #define MATCH_C_AND 0x8c61
 539 #define MASK_C_AND  0xfc63
 540 #define MATCH_C_SUBW 0x9c01
 541 #define MASK_C_SUBW  0xfc63
 542 #define MATCH_C_ADDW 0x9c21
 543 #define MASK_C_ADDW  0xfc63
 544 #define MATCH_C_J 0xa001
 545 #define MASK_C_J  0xe003
 546 #define MATCH_C_BEQZ 0xc001
 547 #define MASK_C_BEQZ  0xe003
 548 #define MATCH_C_BNEZ 0xe001
 549 #define MASK_C_BNEZ  0xe003
 550 #define MATCH_C_SLLI 0x2
 551 #define MASK_C_SLLI  0xe003
 552 #define MATCH_C_FLDSP 0x2002
 553 #define MASK_C_FLDSP  0xe003
 554 #define MATCH_C_LWSP 0x4002
 555 #define MASK_C_LWSP  0xe003
 556 #define MATCH_C_FLWSP 0x6002
 557 #define MASK_C_FLWSP  0xe003
 558 #define MATCH_C_MV 0x8002
 559 #define MASK_C_MV  0xf003
 560 #define MATCH_C_ADD 0x9002
 561 #define MASK_C_ADD  0xf003
 562 #define MATCH_C_FSDSP 0xa002
 563 #define MASK_C_FSDSP  0xe003
 564 #define MATCH_C_SWSP 0xc002
 565 #define MASK_C_SWSP  0xe003
 566 #define MATCH_C_FSWSP 0xe002
 567 #define MASK_C_FSWSP  0xe003
 568 #define MATCH_CUSTOM0 0xb
 569 #define MASK_CUSTOM0  0x707f
 570 #define MATCH_CUSTOM0_RS1 0x200b
 571 #define MASK_CUSTOM0_RS1  0x707f
 572 #define MATCH_CUSTOM0_RS1_RS2 0x300b
 573 #define MASK_CUSTOM0_RS1_RS2  0x707f
 574 #define MATCH_CUSTOM0_RD 0x400b
 575 #define MASK_CUSTOM0_RD  0x707f
 576 #define MATCH_CUSTOM0_RD_RS1 0x600b
 577 #define MASK_CUSTOM0_RD_RS1  0x707f
 578 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
 579 #define MASK_CUSTOM0_RD_RS1_RS2  0x707f
 580 #define MATCH_CUSTOM1 0x2b
 581 #define MASK_CUSTOM1  0x707f
 582 #define MATCH_CUSTOM1_RS1 0x202b
 583 #define MASK_CUSTOM1_RS1  0x707f
 584 #define MATCH_CUSTOM1_RS1_RS2 0x302b
 585 #define MASK_CUSTOM1_RS1_RS2  0x707f
 586 #define MATCH_CUSTOM1_RD 0x402b
 587 #define MASK_CUSTOM1_RD  0x707f
 588 #define MATCH_CUSTOM1_RD_RS1 0x602b
 589 #define MASK_CUSTOM1_RD_RS1  0x707f
 590 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
 591 #define MASK_CUSTOM1_RD_RS1_RS2  0x707f
 592 #define MATCH_CUSTOM2 0x5b
 593 #define MASK_CUSTOM2  0x707f
 594 #define MATCH_CUSTOM2_RS1 0x205b
 595 #define MASK_CUSTOM2_RS1  0x707f
 596 #define MATCH_CUSTOM2_RS1_RS2 0x305b
 597 #define MASK_CUSTOM2_RS1_RS2  0x707f
 598 #define MATCH_CUSTOM2_RD 0x405b
 599 #define MASK_CUSTOM2_RD  0x707f
 600 #define MATCH_CUSTOM2_RD_RS1 0x605b
 601 #define MASK_CUSTOM2_RD_RS1  0x707f
 602 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
 603 #define MASK_CUSTOM2_RD_RS1_RS2  0x707f
 604 #define MATCH_CUSTOM3 0x7b
 605 #define MASK_CUSTOM3  0x707f
 606 #define MATCH_CUSTOM3_RS1 0x207b
 607 #define MASK_CUSTOM3_RS1  0x707f
 608 #define MATCH_CUSTOM3_RS1_RS2 0x307b
 609 #define MASK_CUSTOM3_RS1_RS2  0x707f
 610 #define MATCH_CUSTOM3_RD 0x407b
 611 #define MASK_CUSTOM3_RD  0x707f
 612 #define MATCH_CUSTOM3_RD_RS1 0x607b
 613 #define MASK_CUSTOM3_RD_RS1  0x707f
 614 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
 615 #define MASK_CUSTOM3_RD_RS1_RS2  0x707f
 616 #define CSR_FFLAGS 0x1
 617 #define CSR_FRM 0x2
 618 #define CSR_FCSR 0x3
 619 #define CSR_CYCLE 0xc00
 620 #define CSR_TIME 0xc01
 621 #define CSR_INSTRET 0xc02
 622 #define CSR_STATS 0xc0
 623 #define CSR_UARCH0 0xcc0
 624 #define CSR_UARCH1 0xcc1
 625 #define CSR_UARCH2 0xcc2
 626 #define CSR_UARCH3 0xcc3
 627 #define CSR_UARCH4 0xcc4
 628 #define CSR_UARCH5 0xcc5
 629 #define CSR_UARCH6 0xcc6
 630 #define CSR_UARCH7 0xcc7
 631 #define CSR_UARCH8 0xcc8
 632 #define CSR_UARCH9 0xcc9
 633 #define CSR_UARCH10 0xcca
 634 #define CSR_UARCH11 0xccb
 635 #define CSR_UARCH12 0xccc
 636 #define CSR_UARCH13 0xccd
 637 #define CSR_UARCH14 0xcce
 638 #define CSR_UARCH15 0xccf
 639 #define CSR_SSTATUS 0x100
 640 #define CSR_STVEC 0x101
 641 #define CSR_SIE 0x104
 642 #define CSR_SSCRATCH 0x140
 643 #define CSR_SEPC 0x141
 644 #define CSR_SCAUSE 0x142
 645 #define CSR_SBADADDR 0x143
 646 #define CSR_SIP 0x144
 647 #define CSR_SPTBR 0x180
 648 #define CSR_SASID 0x181
 649 #define CSR_CYCLEW 0x900
 650 #define CSR_TIMEW 0x901
 651 #define CSR_INSTRETW 0x902
 652 #define CSR_STIME 0xd01
 653 #define CSR_STIMEW 0xa01
 654 #define CSR_MSTATUS 0x300
 655 #define CSR_MTVEC 0x301
 656 #define CSR_MEDELEG 0x302
 657 #define CSR_MIDELEG 0x303
 658 #define CSR_MIE 0x304
 659 #define CSR_MTIMECMP 0x321
 660 #define CSR_MSCRATCH 0x340
 661 #define CSR_MEPC 0x341
 662 #define CSR_MCAUSE 0x342
 663 #define CSR_MBADADDR 0x343
 664 #define CSR_MIP 0x344
 665 #define CSR_MTIME 0x701
 666 #define CSR_MCPUID 0xf00
 667 #define CSR_MIMPID 0xf01
 668 #define CSR_MHARTID 0xf10
 669 #define CSR_MTOHOST 0x780
 670 #define CSR_MFROMHOST 0x781
 671 #define CSR_MRESET 0x782
 672 #define CSR_MIPI 0x783
 673 #define CSR_MIOBASE 0x784
 674 #define CSR_CYCLEH 0xc80
 675 #define CSR_TIMEH 0xc81
 676 #define CSR_INSTRETH 0xc82
 677 #define CSR_CYCLEHW 0x980
 678 #define CSR_TIMEHW 0x981
 679 #define CSR_INSTRETHW 0x982
 680 #define CSR_STIMEH 0xd81
 681 #define CSR_STIMEHW 0xa81
 682 #define CSR_MTIMECMPH 0x361
 683 #define CSR_MTIMEH 0x741
 684 #define CAUSE_MISALIGNED_FETCH 0x0
 685 #define CAUSE_FAULT_FETCH 0x1
 686 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
 687 #define CAUSE_BREAKPOINT 0x3
 688 #define CAUSE_MISALIGNED_LOAD 0x4
 689 #define CAUSE_FAULT_LOAD 0x5
 690 #define CAUSE_MISALIGNED_STORE 0x6
 691 #define CAUSE_FAULT_STORE 0x7
 692 #define CAUSE_USER_ECALL 0x8
 693 #define CAUSE_SUPERVISOR_ECALL 0x9
 694 #define CAUSE_HYPERVISOR_ECALL 0xa
 695 #define CAUSE_MACHINE_ECALL 0xb
 696 #endif
 697 #ifdef DECLARE_INSN
 698 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
 699 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
 700 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
 701 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
 702 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
 703 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
 704 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
 705 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
 706 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
 707 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
 708 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
 709 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
 710 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
 711 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
 712 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
 713 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
 714 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
 715 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
 716 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
 717 DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
 718 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
 719 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
 720 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
 721 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
 722 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
 723 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
 724 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
 725 DECLARE_INSN(or, MATCH_OR, MASK_OR)
 726 DECLARE_INSN(and, MATCH_AND, MASK_AND)
 727 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
 728 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
 729 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
 730 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
 731 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
 732 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
 733 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
 734 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
 735 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
 736 DECLARE_INSN(lb, MATCH_LB, MASK_LB)
 737 DECLARE_INSN(lh, MATCH_LH, MASK_LH)
 738 DECLARE_INSN(lw, MATCH_LW, MASK_LW)
 739 DECLARE_INSN(ld, MATCH_LD, MASK_LD)
 740 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
 741 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
 742 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
 743 DECLARE_INSN(sb, MATCH_SB, MASK_SB)
 744 DECLARE_INSN(sh, MATCH_SH, MASK_SH)
 745 DECLARE_INSN(sw, MATCH_SW, MASK_SW)
 746 DECLARE_INSN(sd, MATCH_SD, MASK_SD)
 747 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
 748 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
 749 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
 750 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
 751 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
 752 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
 753 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
 754 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
 755 DECLARE_INSN(rem, MATCH_REM, MASK_REM)
 756 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
 757 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
 758 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
 759 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
 760 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
 761 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
 762 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
 763 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
 764 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
 765 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
 766 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
 767 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
 768 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
 769 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
 770 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
 771 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
 772 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
 773 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
 774 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
 775 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
 776 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
 777 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
 778 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
 779 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
 780 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
 781 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
 782 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
 783 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
 784 DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
 785 DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
 786 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
 787 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
 788 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
 789 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
 790 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
 791 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
 792 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
 793 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
 794 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
 795 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
 796 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
 797 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
 798 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
 799 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
 800 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
 801 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
 802 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
 803 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
 804 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
 805 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
 806 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
 807 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
 808 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
 809 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
 810 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
 811 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
 812 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
 813 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
 814 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
 815 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
 816 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
 817 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
 818 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
 819 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
 820 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
 821 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
 822 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
 823 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
 824 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
 825 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
 826 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
 827 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
 828 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
 829 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
 830 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
 831 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
 832 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
 833 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
 834 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
 835 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
 836 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
 837 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
 838 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
 839 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
 840 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
 841 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
 842 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
 843 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
 844 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
 845 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
 846 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
 847 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
 848 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
 849 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
 850 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
 851 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
 852 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
 853 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
 854 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
 855 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
 856 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
 857 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
 858 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
 859 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
 860 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
 861 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
 862 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
 863 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
 864 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
 865 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
 866 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
 867 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
 868 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
 869 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
 870 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
 871 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
 872 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
 873 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
 874 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
 875 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
 876 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
 877 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
 878 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
 879 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
 880 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
 881 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
 882 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
 883 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
 884 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
 885 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
 886 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
 887 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
 888 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
 889 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
 890 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
 891 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
 892 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
 893 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
 894 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
 895 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
 896 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
 897 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
 898 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
 899 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
 900 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
 901 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
 902 DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
 903 DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
 904 DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
 905 DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
 906 DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
 907 DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
 908 DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
 909 DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
 910 DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
 911 DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
 912 DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
 913 DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
 914 DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
 915 DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
 916 DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
 917 DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
 918 DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
 919 DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
 920 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
 921 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 922 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
 923 #endif
 924 #ifdef DECLARE_CSR
 925 DECLARE_CSR(fflags, CSR_FFLAGS)
 926 DECLARE_CSR(frm, CSR_FRM)
 927 DECLARE_CSR(fcsr, CSR_FCSR)
 928 DECLARE_CSR(cycle, CSR_CYCLE)
 929 DECLARE_CSR(time, CSR_TIME)
 930 DECLARE_CSR(instret, CSR_INSTRET)
 931 DECLARE_CSR(stats, CSR_STATS)
 932 DECLARE_CSR(uarch0, CSR_UARCH0)
 933 DECLARE_CSR(uarch1, CSR_UARCH1)
 934 DECLARE_CSR(uarch2, CSR_UARCH2)
 935 DECLARE_CSR(uarch3, CSR_UARCH3)
 936 DECLARE_CSR(uarch4, CSR_UARCH4)
 937 DECLARE_CSR(uarch5, CSR_UARCH5)
 938 DECLARE_CSR(uarch6, CSR_UARCH6)
 939 DECLARE_CSR(uarch7, CSR_UARCH7)
 940 DECLARE_CSR(uarch8, CSR_UARCH8)
 941 DECLARE_CSR(uarch9, CSR_UARCH9)
 942 DECLARE_CSR(uarch10, CSR_UARCH10)
 943 DECLARE_CSR(uarch11, CSR_UARCH11)
 944 DECLARE_CSR(uarch12, CSR_UARCH12)
 945 DECLARE_CSR(uarch13, CSR_UARCH13)
 946 DECLARE_CSR(uarch14, CSR_UARCH14)
 947 DECLARE_CSR(uarch15, CSR_UARCH15)
 948 DECLARE_CSR(sstatus, CSR_SSTATUS)
 949 DECLARE_CSR(stvec, CSR_STVEC)
 950 DECLARE_CSR(sie, CSR_SIE)
 951 DECLARE_CSR(sscratch, CSR_SSCRATCH)
 952 DECLARE_CSR(sepc, CSR_SEPC)
 953 DECLARE_CSR(scause, CSR_SCAUSE)
 954 DECLARE_CSR(sbadaddr, CSR_SBADADDR)
 955 DECLARE_CSR(sip, CSR_SIP)
 956 DECLARE_CSR(sptbr, CSR_SPTBR)
 957 DECLARE_CSR(sasid, CSR_SASID)
 958 DECLARE_CSR(cyclew, CSR_CYCLEW)
 959 DECLARE_CSR(timew, CSR_TIMEW)
 960 DECLARE_CSR(instretw, CSR_INSTRETW)
 961 DECLARE_CSR(stime, CSR_STIME)
 962 DECLARE_CSR(stimew, CSR_STIMEW)
 963 DECLARE_CSR(mstatus, CSR_MSTATUS)
 964 DECLARE_CSR(mtvec, CSR_MTVEC)
 965 DECLARE_CSR(medeleg, CSR_MEDELEG)
 966 DECLARE_CSR(mideleg, CSR_MIDELEG)
 967 DECLARE_CSR(mie, CSR_MIE)
 968 DECLARE_CSR(mtimecmp, CSR_MTIMECMP)
 969 DECLARE_CSR(mscratch, CSR_MSCRATCH)
 970 DECLARE_CSR(mepc, CSR_MEPC)
 971 DECLARE_CSR(mcause, CSR_MCAUSE)
 972 DECLARE_CSR(mbadaddr, CSR_MBADADDR)
 973 DECLARE_CSR(mip, CSR_MIP)
 974 DECLARE_CSR(mtime, CSR_MTIME)
 975 DECLARE_CSR(mcpuid, CSR_MCPUID)
 976 DECLARE_CSR(mimpid, CSR_MIMPID)
 977 DECLARE_CSR(mhartid, CSR_MHARTID)
 978 DECLARE_CSR(mtohost, CSR_MTOHOST)
 979 DECLARE_CSR(mfromhost, CSR_MFROMHOST)
 980 DECLARE_CSR(mreset, CSR_MRESET)
 981 DECLARE_CSR(mipi, CSR_MIPI)
 982 DECLARE_CSR(miobase, CSR_MIOBASE)
 983 DECLARE_CSR(cycleh, CSR_CYCLEH)
 984 DECLARE_CSR(timeh, CSR_TIMEH)
 985 DECLARE_CSR(instreth, CSR_INSTRETH)
 986 DECLARE_CSR(cyclehw, CSR_CYCLEHW)
 987 DECLARE_CSR(timehw, CSR_TIMEHW)
 988 DECLARE_CSR(instrethw, CSR_INSTRETHW)
 989 DECLARE_CSR(stimeh, CSR_STIMEH)
 990 DECLARE_CSR(stimehw, CSR_STIMEHW)
 991 DECLARE_CSR(mtimecmph, CSR_MTIMECMPH)
 992 DECLARE_CSR(mtimeh, CSR_MTIMEH)
 993 #endif
 994 #ifdef DECLARE_CAUSE
 995 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
 996 DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
 997 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
 998 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
 999 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
1000 DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
1001 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
1002 DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
1003 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
1004 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
1005 DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
1006 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
1007 #endif