riscv/encoding.h

   1 // See LICENSE for license details.
   2
   3 #ifndef RISCV_CSR_ENCODING_H
   4 #define RISCV_CSR_ENCODING_H
   5
   6 #define MSTATUS_UIE         0x00000001
   7 #define MSTATUS_SIE         0x00000002
   8 #define MSTATUS_HIE         0x00000004
   9 #define MSTATUS_MIE         0x00000008
  10 #define MSTATUS_UPIE        0x00000010
  11 #define MSTATUS_SPIE        0x00000020
  12 #define MSTATUS_HPIE        0x00000040
  13 #define MSTATUS_MPIE        0x00000080
  14 #define MSTATUS_SPP         0x00000100
  15 #define MSTATUS_HPP         0x00000600
  16 #define MSTATUS_MPP         0x00001800
  17 #define MSTATUS_FS          0x00006000
  18 #define MSTATUS_XS          0x00018000
  19 #define MSTATUS_MPRV        0x00020000
  20 #define MSTATUS_PUM         0x00040000
  21 #define MSTATUS_MXR         0x00080000
  22 #define MSTATUS_VM          0x1F000000
  23 #define MSTATUS32_SD        0x80000000
  24 #define MSTATUS64_SD        0x8000000000000000
  25
  26 #define SSTATUS_UIE         0x00000001
  27 #define SSTATUS_SIE         0x00000002
  28 #define SSTATUS_UPIE        0x00000010
  29 #define SSTATUS_SPIE        0x00000020
  30 #define SSTATUS_SPP         0x00000100
  31 #define SSTATUS_FS          0x00006000
  32 #define SSTATUS_XS          0x00018000
  33 #define SSTATUS_PUM         0x00040000
  34 #define SSTATUS32_SD        0x80000000
  35 #define SSTATUS64_SD        0x8000000000000000
  36
  37 #define DCSR_XDEBUGVER      (3U<<30)
  38 #define DCSR_NDRESET        (1<<29)
  39 #define DCSR_FULLRESET      (1<<28)
  40 #define DCSR_EBREAKM        (1<<15)
  41 #define DCSR_EBREAKH        (1<<14)
  42 #define DCSR_EBREAKS        (1<<13)
  43 #define DCSR_EBREAKU        (1<<12)
  44 #define DCSR_STOPCYCLE      (1<<10)
  45 #define DCSR_STOPTIME       (1<<9)
  46 #define DCSR_CAUSE          (7<<6)
  47 #define DCSR_DEBUGINT       (1<<5)
  48 #define DCSR_HALT           (1<<3)
  49 #define DCSR_STEP           (1<<2)
  50 #define DCSR_PRV            (3<<0)
  51
  52 #define DCSR_CAUSE_NONE     0
  53 #define DCSR_CAUSE_SWBP     1
  54 #define DCSR_CAUSE_HWBP     2
  55 #define DCSR_CAUSE_DEBUGINT 3
  56 #define DCSR_CAUSE_STEP     4
  57 #define DCSR_CAUSE_HALT     5
  58
  59 #define MCONTROL_TYPE(xlen)    (0xfULL<<((xlen)-4))
  60 #define MCONTROL_DMODE(xlen)   (1ULL<<((xlen)-5))
  61 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
  62
  63 #define MCONTROL_SELECT     (1<<19)
  64 #define MCONTROL_TIMING     (1<<18)
  65 #define MCONTROL_ACTION     (0x3f<<12)
  66 #define MCONTROL_CHAIN      (1<<11)
  67 #define MCONTROL_MATCH      (0xf<<7)
  68 #define MCONTROL_M          (1<<6)
  69 #define MCONTROL_H          (1<<5)
  70 #define MCONTROL_S          (1<<4)
  71 #define MCONTROL_U          (1<<3)
  72 #define MCONTROL_EXECUTE    (1<<2)
  73 #define MCONTROL_STORE      (1<<1)
  74 #define MCONTROL_LOAD       (1<<0)
  75
  76 #define MCONTROL_ACTION_DEBUG_EXCEPTION   0
  77 #define MCONTROL_ACTION_DEBUG_MODE        1
  78 #define MCONTROL_ACTION_TRACE_START       2
  79 #define MCONTROL_ACTION_TRACE_STOP        3
  80 #define MCONTROL_ACTION_TRACE_EMIT        4
  81
  82 #define MCONTROL_MATCH_EQUAL     0
  83 #define MCONTROL_MATCH_NAPOT     1
  84 #define MCONTROL_MATCH_GE        2
  85 #define MCONTROL_MATCH_LT        3
  86 #define MCONTROL_MATCH_MASK_LOW  4
  87 #define MCONTROL_MATCH_MASK_HIGH 5
  88
  89 #define MIP_SSIP            (1 << IRQ_S_SOFT)
  90 #define MIP_HSIP            (1 << IRQ_H_SOFT)
  91 #define MIP_MSIP            (1 << IRQ_M_SOFT)
  92 #define MIP_STIP            (1 << IRQ_S_TIMER)
  93 #define MIP_HTIP            (1 << IRQ_H_TIMER)
  94 #define MIP_MTIP            (1 << IRQ_M_TIMER)
  95 #define MIP_SEIP            (1 << IRQ_S_EXT)
  96 #define MIP_HEIP            (1 << IRQ_H_EXT)
  97 #define MIP_MEIP            (1 << IRQ_M_EXT)
  98
  99 #define SIP_SSIP MIP_SSIP
 100 #define SIP_STIP MIP_STIP
 101
 102 #define PRV_U 0
 103 #define PRV_S 1
 104 #define PRV_H 2
 105 #define PRV_M 3
 106
 107 #define VM_MBARE 0
 108 #define VM_MBB   1
 109 #define VM_MBBID 2
 110 #define VM_SV32  8
 111 #define VM_SV39  9
 112 #define VM_SV48  10
 113
 114 #define IRQ_S_SOFT   1
 115 #define IRQ_H_SOFT   2
 116 #define IRQ_M_SOFT   3
 117 #define IRQ_S_TIMER  5
 118 #define IRQ_H_TIMER  6
 119 #define IRQ_M_TIMER  7
 120 #define IRQ_S_EXT    9
 121 #define IRQ_H_EXT    10
 122 #define IRQ_M_EXT    11
 123 #define IRQ_COP      12
 124 #define IRQ_HOST     13
 125
 126 #define DEFAULT_RSTVEC     0x00001000
 127 #define DEFAULT_NMIVEC     0x00001004
 128 #define DEFAULT_MTVEC      0x00001010
 129 #define CONFIG_STRING_ADDR 0x0000100C
 130 #define EXT_IO_BASE        0x40000000
 131 #define DRAM_BASE          0x80000000
 132
 133 // page table entry (PTE) fields
 134 #define PTE_V     0x001 // Valid
 135 #define PTE_R     0x002 // Read
 136 #define PTE_W     0x004 // Write
 137 #define PTE_X     0x008 // Execute
 138 #define PTE_U     0x010 // User
 139 #define PTE_G     0x020 // Global
 140 #define PTE_A     0x040 // Accessed
 141 #define PTE_D     0x080 // Dirty
 142 #define PTE_SOFT  0x300 // Reserved for Software
 143
 144 #define PTE_PPN_SHIFT 10
 145
 146 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
 147
 148 #ifdef __riscv
 149
 150 #ifdef __riscv64
 151 # define MSTATUS_SD MSTATUS64_SD
 152 # define SSTATUS_SD SSTATUS64_SD
 153 # define RISCV_PGLEVEL_BITS 9
 154 #else
 155 # define MSTATUS_SD MSTATUS32_SD
 156 # define SSTATUS_SD SSTATUS32_SD
 157 # define RISCV_PGLEVEL_BITS 10
 158 #endif
 159 #define RISCV_PGSHIFT 12
 160 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
 161
 162 #ifndef __ASSEMBLER__
 163
 164 #ifdef __GNUC__
 165
 166 #define read_csr(reg) ({ unsigned long __tmp; \
 167   asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
 168   __tmp; })
 169
 170 #define write_csr(reg, val) ({ \
 171   if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
 172     asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
 173   else \
 174     asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
 175
 176 #define swap_csr(reg, val) ({ unsigned long __tmp; \
 177   if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
 178     asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
 179   else \
 180     asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
 181   __tmp; })
 182
 183 #define set_csr(reg, bit) ({ unsigned long __tmp; \
 184   if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
 185     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 186   else \
 187     asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
 188   __tmp; })
 189
 190 #define clear_csr(reg, bit) ({ unsigned long __tmp; \
 191   if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
 192     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
 193   else \
 194     asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
 195   __tmp; })
 196
 197 #define rdtime() read_csr(time)
 198 #define rdcycle() read_csr(cycle)
 199 #define rdinstret() read_csr(instret)
 200
 201 #endif
 202
 203 #endif
 204
 205 #endif
 206
 207 #endif
 208 /* Automatically generated by parse-opcodes */
 209 #ifndef RISCV_ENCODING_H
 210 #define RISCV_ENCODING_H
 211 #define MATCH_BEQ 0x63
 212 #define MASK_BEQ  0x707f
 213 #define MATCH_BNE 0x1063
 214 #define MASK_BNE  0x707f
 215 #define MATCH_BLT 0x4063
 216 #define MASK_BLT  0x707f
 217 #define MATCH_BGE 0x5063
 218 #define MASK_BGE  0x707f
 219 #define MATCH_BLTU 0x6063
 220 #define MASK_BLTU  0x707f
 221 #define MATCH_BGEU 0x7063
 222 #define MASK_BGEU  0x707f
 223 #define MATCH_JALR 0x67
 224 #define MASK_JALR  0x707f
 225 #define MATCH_JAL 0x6f
 226 #define MASK_JAL  0x7f
 227 #define MATCH_LUI 0x37
 228 #define MASK_LUI  0x7f
 229 #define MATCH_AUIPC 0x17
 230 #define MASK_AUIPC  0x7f
 231 #define MATCH_ADDI 0x13
 232 #define MASK_ADDI  0x707f
 233 #define MATCH_SLLI 0x1013
 234 #define MASK_SLLI  0xfc00707f
 235 #define MATCH_SLTI 0x2013
 236 #define MASK_SLTI  0x707f
 237 #define MATCH_SLTIU 0x3013
 238 #define MASK_SLTIU  0x707f
 239 #define MATCH_XORI 0x4013
 240 #define MASK_XORI  0x707f
 241 #define MATCH_SRLI 0x5013
 242 #define MASK_SRLI  0xfc00707f
 243 #define MATCH_SRAI 0x40005013
 244 #define MASK_SRAI  0xfc00707f
 245 #define MATCH_ORI 0x6013
 246 #define MASK_ORI  0x707f
 247 #define MATCH_ANDI 0x7013
 248 #define MASK_ANDI  0x707f
 249 #define MATCH_ADD 0x33
 250 #define MASK_ADD  0xfe00707f
 251 #define MATCH_SUB 0x40000033
 252 #define MASK_SUB  0xfe00707f
 253 #define MATCH_SLL 0x1033
 254 #define MASK_SLL  0xfe00707f
 255 #define MATCH_SLT 0x2033
 256 #define MASK_SLT  0xfe00707f
 257 #define MATCH_SLTU 0x3033
 258 #define MASK_SLTU  0xfe00707f
 259 #define MATCH_XOR 0x4033
 260 #define MASK_XOR  0xfe00707f
 261 #define MATCH_SRL 0x5033
 262 #define MASK_SRL  0xfe00707f
 263 #define MATCH_SRA 0x40005033
 264 #define MASK_SRA  0xfe00707f
 265 #define MATCH_OR 0x6033
 266 #define MASK_OR  0xfe00707f
 267 #define MATCH_AND 0x7033
 268 #define MASK_AND  0xfe00707f
 269 #define MATCH_ADDIW 0x1b
 270 #define MASK_ADDIW  0x707f
 271 #define MATCH_SLLIW 0x101b
 272 #define MASK_SLLIW  0xfe00707f
 273 #define MATCH_SRLIW 0x501b
 274 #define MASK_SRLIW  0xfe00707f
 275 #define MATCH_SRAIW 0x4000501b
 276 #define MASK_SRAIW  0xfe00707f
 277 #define MATCH_ADDW 0x3b
 278 #define MASK_ADDW  0xfe00707f
 279 #define MATCH_SUBW 0x4000003b
 280 #define MASK_SUBW  0xfe00707f
 281 #define MATCH_SLLW 0x103b
 282 #define MASK_SLLW  0xfe00707f
 283 #define MATCH_SRLW 0x503b
 284 #define MASK_SRLW  0xfe00707f
 285 #define MATCH_SRAW 0x4000503b
 286 #define MASK_SRAW  0xfe00707f
 287 #define MATCH_LB 0x3
 288 #define MASK_LB  0x707f
 289 #define MATCH_LH 0x1003
 290 #define MASK_LH  0x707f
 291 #define MATCH_LW 0x2003
 292 #define MASK_LW  0x707f
 293 #define MATCH_LD 0x3003
 294 #define MASK_LD  0x707f
 295 #define MATCH_LBU 0x4003
 296 #define MASK_LBU  0x707f
 297 #define MATCH_LHU 0x5003
 298 #define MASK_LHU  0x707f
 299 #define MATCH_LWU 0x6003
 300 #define MASK_LWU  0x707f
 301 #define MATCH_SB 0x23
 302 #define MASK_SB  0x707f
 303 #define MATCH_SH 0x1023
 304 #define MASK_SH  0x707f
 305 #define MATCH_SW 0x2023
 306 #define MASK_SW  0x707f
 307 #define MATCH_SD 0x3023
 308 #define MASK_SD  0x707f
 309 #define MATCH_FENCE 0xf
 310 #define MASK_FENCE  0x707f
 311 #define MATCH_FENCE_I 0x100f
 312 #define MASK_FENCE_I  0x707f
 313 #define MATCH_MUL 0x2000033
 314 #define MASK_MUL  0xfe00707f
 315 #define MATCH_MULH 0x2001033
 316 #define MASK_MULH  0xfe00707f
 317 #define MATCH_MULHSU 0x2002033
 318 #define MASK_MULHSU  0xfe00707f
 319 #define MATCH_MULHU 0x2003033
 320 #define MASK_MULHU  0xfe00707f
 321 #define MATCH_DIV 0x2004033
 322 #define MASK_DIV  0xfe00707f
 323 #define MATCH_DIVU 0x2005033
 324 #define MASK_DIVU  0xfe00707f
 325 #define MATCH_REM 0x2006033
 326 #define MASK_REM  0xfe00707f
 327 #define MATCH_REMU 0x2007033
 328 #define MASK_REMU  0xfe00707f
 329 #define MATCH_MULW 0x200003b
 330 #define MASK_MULW  0xfe00707f
 331 #define MATCH_DIVW 0x200403b
 332 #define MASK_DIVW  0xfe00707f
 333 #define MATCH_DIVUW 0x200503b
 334 #define MASK_DIVUW  0xfe00707f
 335 #define MATCH_REMW 0x200603b
 336 #define MASK_REMW  0xfe00707f
 337 #define MATCH_REMUW 0x200703b
 338 #define MASK_REMUW  0xfe00707f
 339 #define MATCH_AMOADD_W 0x202f
 340 #define MASK_AMOADD_W  0xf800707f
 341 #define MATCH_AMOXOR_W 0x2000202f
 342 #define MASK_AMOXOR_W  0xf800707f
 343 #define MATCH_AMOOR_W 0x4000202f
 344 #define MASK_AMOOR_W  0xf800707f
 345 #define MATCH_AMOAND_W 0x6000202f
 346 #define MASK_AMOAND_W  0xf800707f
 347 #define MATCH_AMOMIN_W 0x8000202f
 348 #define MASK_AMOMIN_W  0xf800707f
 349 #define MATCH_AMOMAX_W 0xa000202f
 350 #define MASK_AMOMAX_W  0xf800707f
 351 #define MATCH_AMOMINU_W 0xc000202f
 352 #define MASK_AMOMINU_W  0xf800707f
 353 #define MATCH_AMOMAXU_W 0xe000202f
 354 #define MASK_AMOMAXU_W  0xf800707f
 355 #define MATCH_AMOSWAP_W 0x800202f
 356 #define MASK_AMOSWAP_W  0xf800707f
 357 #define MATCH_LR_W 0x1000202f
 358 #define MASK_LR_W  0xf9f0707f
 359 #define MATCH_SC_W 0x1800202f
 360 #define MASK_SC_W  0xf800707f
 361 #define MATCH_AMOADD_D 0x302f
 362 #define MASK_AMOADD_D  0xf800707f
 363 #define MATCH_AMOXOR_D 0x2000302f
 364 #define MASK_AMOXOR_D  0xf800707f
 365 #define MATCH_AMOOR_D 0x4000302f
 366 #define MASK_AMOOR_D  0xf800707f
 367 #define MATCH_AMOAND_D 0x6000302f
 368 #define MASK_AMOAND_D  0xf800707f
 369 #define MATCH_AMOMIN_D 0x8000302f
 370 #define MASK_AMOMIN_D  0xf800707f
 371 #define MATCH_AMOMAX_D 0xa000302f
 372 #define MASK_AMOMAX_D  0xf800707f
 373 #define MATCH_AMOMINU_D 0xc000302f
 374 #define MASK_AMOMINU_D  0xf800707f
 375 #define MATCH_AMOMAXU_D 0xe000302f
 376 #define MASK_AMOMAXU_D  0xf800707f
 377 #define MATCH_AMOSWAP_D 0x800302f
 378 #define MASK_AMOSWAP_D  0xf800707f
 379 #define MATCH_LR_D 0x1000302f
 380 #define MASK_LR_D  0xf9f0707f
 381 #define MATCH_SC_D 0x1800302f
 382 #define MASK_SC_D  0xf800707f
 383 #define MATCH_ECALL 0x73
 384 #define MASK_ECALL  0xffffffff
 385 #define MATCH_EBREAK 0x100073
 386 #define MASK_EBREAK  0xffffffff
 387 #define MATCH_URET 0x200073
 388 #define MASK_URET  0xffffffff
 389 #define MATCH_SRET 0x10200073
 390 #define MASK_SRET  0xffffffff
 391 #define MATCH_HRET 0x20200073
 392 #define MASK_HRET  0xffffffff
 393 #define MATCH_MRET 0x30200073
 394 #define MASK_MRET  0xffffffff
 395 #define MATCH_DRET 0x7b200073
 396 #define MASK_DRET  0xffffffff
 397 #define MATCH_SFENCE_VM 0x10400073
 398 #define MASK_SFENCE_VM  0xfff07fff
 399 #define MATCH_WFI 0x10500073
 400 #define MASK_WFI  0xffffffff
 401 #define MATCH_CSRRW 0x1073
 402 #define MASK_CSRRW  0x707f
 403 #define MATCH_CSRRS 0x2073
 404 #define MASK_CSRRS  0x707f
 405 #define MATCH_CSRRC 0x3073
 406 #define MASK_CSRRC  0x707f
 407 #define MATCH_CSRRWI 0x5073
 408 #define MASK_CSRRWI  0x707f
 409 #define MATCH_CSRRSI 0x6073
 410 #define MASK_CSRRSI  0x707f
 411 #define MATCH_CSRRCI 0x7073
 412 #define MASK_CSRRCI  0x707f
 413 #define MATCH_FADD_S 0x53
 414 #define MASK_FADD_S  0xfe00007f
 415 #define MATCH_FSUB_S 0x8000053
 416 #define MASK_FSUB_S  0xfe00007f
 417 #define MATCH_FMUL_S 0x10000053
 418 #define MASK_FMUL_S  0xfe00007f
 419 #define MATCH_FDIV_S 0x18000053
 420 #define MASK_FDIV_S  0xfe00007f
 421 #define MATCH_FSGNJ_S 0x20000053
 422 #define MASK_FSGNJ_S  0xfe00707f
 423 #define MATCH_FSGNJN_S 0x20001053
 424 #define MASK_FSGNJN_S  0xfe00707f
 425 #define MATCH_FSGNJX_S 0x20002053
 426 #define MASK_FSGNJX_S  0xfe00707f
 427 #define MATCH_FMIN_S 0x28000053
 428 #define MASK_FMIN_S  0xfe00707f
 429 #define MATCH_FMAX_S 0x28001053
 430 #define MASK_FMAX_S  0xfe00707f
 431 #define MATCH_FSQRT_S 0x58000053
 432 #define MASK_FSQRT_S  0xfff0007f
 433 #define MATCH_FADD_D 0x2000053
 434 #define MASK_FADD_D  0xfe00007f
 435 #define MATCH_FSUB_D 0xa000053
 436 #define MASK_FSUB_D  0xfe00007f
 437 #define MATCH_FMUL_D 0x12000053
 438 #define MASK_FMUL_D  0xfe00007f
 439 #define MATCH_FDIV_D 0x1a000053
 440 #define MASK_FDIV_D  0xfe00007f
 441 #define MATCH_FSGNJ_D 0x22000053
 442 #define MASK_FSGNJ_D  0xfe00707f
 443 #define MATCH_FSGNJN_D 0x22001053
 444 #define MASK_FSGNJN_D  0xfe00707f
 445 #define MATCH_FSGNJX_D 0x22002053
 446 #define MASK_FSGNJX_D  0xfe00707f
 447 #define MATCH_FMIN_D 0x2a000053
 448 #define MASK_FMIN_D  0xfe00707f
 449 #define MATCH_FMAX_D 0x2a001053
 450 #define MASK_FMAX_D  0xfe00707f
 451 #define MATCH_FCVT_S_D 0x40100053
 452 #define MASK_FCVT_S_D  0xfff0007f
 453 #define MATCH_FCVT_D_S 0x42000053
 454 #define MASK_FCVT_D_S  0xfff0007f
 455 #define MATCH_FSQRT_D 0x5a000053
 456 #define MASK_FSQRT_D  0xfff0007f
 457 #define MATCH_FLE_S 0xa0000053
 458 #define MASK_FLE_S  0xfe00707f
 459 #define MATCH_FLT_S 0xa0001053
 460 #define MASK_FLT_S  0xfe00707f
 461 #define MATCH_FEQ_S 0xa0002053
 462 #define MASK_FEQ_S  0xfe00707f
 463 #define MATCH_FLE_D 0xa2000053
 464 #define MASK_FLE_D  0xfe00707f
 465 #define MATCH_FLT_D 0xa2001053
 466 #define MASK_FLT_D  0xfe00707f
 467 #define MATCH_FEQ_D 0xa2002053
 468 #define MASK_FEQ_D  0xfe00707f
 469 #define MATCH_FCVT_W_S 0xc0000053
 470 #define MASK_FCVT_W_S  0xfff0007f
 471 #define MATCH_FCVT_WU_S 0xc0100053
 472 #define MASK_FCVT_WU_S  0xfff0007f
 473 #define MATCH_FCVT_L_S 0xc0200053
 474 #define MASK_FCVT_L_S  0xfff0007f
 475 #define MATCH_FCVT_LU_S 0xc0300053
 476 #define MASK_FCVT_LU_S  0xfff0007f
 477 #define MATCH_FMV_X_S 0xe0000053
 478 #define MASK_FMV_X_S  0xfff0707f
 479 #define MATCH_FCLASS_S 0xe0001053
 480 #define MASK_FCLASS_S  0xfff0707f
 481 #define MATCH_FCVT_W_D 0xc2000053
 482 #define MASK_FCVT_W_D  0xfff0007f
 483 #define MATCH_FCVT_WU_D 0xc2100053
 484 #define MASK_FCVT_WU_D  0xfff0007f
 485 #define MATCH_FCVT_L_D 0xc2200053
 486 #define MASK_FCVT_L_D  0xfff0007f
 487 #define MATCH_FCVT_LU_D 0xc2300053
 488 #define MASK_FCVT_LU_D  0xfff0007f
 489 #define MATCH_FMV_X_D 0xe2000053
 490 #define MASK_FMV_X_D  0xfff0707f
 491 #define MATCH_FCLASS_D 0xe2001053
 492 #define MASK_FCLASS_D  0xfff0707f
 493 #define MATCH_FCVT_S_W 0xd0000053
 494 #define MASK_FCVT_S_W  0xfff0007f
 495 #define MATCH_FCVT_S_WU 0xd0100053
 496 #define MASK_FCVT_S_WU  0xfff0007f
 497 #define MATCH_FCVT_S_L 0xd0200053
 498 #define MASK_FCVT_S_L  0xfff0007f
 499 #define MATCH_FCVT_S_LU 0xd0300053
 500 #define MASK_FCVT_S_LU  0xfff0007f
 501 #define MATCH_FMV_S_X 0xf0000053
 502 #define MASK_FMV_S_X  0xfff0707f
 503 #define MATCH_FCVT_D_W 0xd2000053
 504 #define MASK_FCVT_D_W  0xfff0007f
 505 #define MATCH_FCVT_D_WU 0xd2100053
 506 #define MASK_FCVT_D_WU  0xfff0007f
 507 #define MATCH_FCVT_D_L 0xd2200053
 508 #define MASK_FCVT_D_L  0xfff0007f
 509 #define MATCH_FCVT_D_LU 0xd2300053
 510 #define MASK_FCVT_D_LU  0xfff0007f
 511 #define MATCH_FMV_D_X 0xf2000053
 512 #define MASK_FMV_D_X  0xfff0707f
 513 #define MATCH_FLW 0x2007
 514 #define MASK_FLW  0x707f
 515 #define MATCH_FLD 0x3007
 516 #define MASK_FLD  0x707f
 517 #define MATCH_FSW 0x2027
 518 #define MASK_FSW  0x707f
 519 #define MATCH_FSD 0x3027
 520 #define MASK_FSD  0x707f
 521 #define MATCH_FMADD_S 0x43
 522 #define MASK_FMADD_S  0x600007f
 523 #define MATCH_FMSUB_S 0x47
 524 #define MASK_FMSUB_S  0x600007f
 525 #define MATCH_FNMSUB_S 0x4b
 526 #define MASK_FNMSUB_S  0x600007f
 527 #define MATCH_FNMADD_S 0x4f
 528 #define MASK_FNMADD_S  0x600007f
 529 #define MATCH_FMADD_D 0x2000043
 530 #define MASK_FMADD_D  0x600007f
 531 #define MATCH_FMSUB_D 0x2000047
 532 #define MASK_FMSUB_D  0x600007f
 533 #define MATCH_FNMSUB_D 0x200004b
 534 #define MASK_FNMSUB_D  0x600007f
 535 #define MATCH_FNMADD_D 0x200004f
 536 #define MASK_FNMADD_D  0x600007f
 537 #define MATCH_C_NOP 0x1
 538 #define MASK_C_NOP  0xffff
 539 #define MATCH_C_ADDI16SP 0x6101
 540 #define MASK_C_ADDI16SP  0xef83
 541 #define MATCH_C_JR 0x8002
 542 #define MASK_C_JR  0xf07f
 543 #define MATCH_C_JALR 0x9002
 544 #define MASK_C_JALR  0xf07f
 545 #define MATCH_C_EBREAK 0x9002
 546 #define MASK_C_EBREAK  0xffff
 547 #define MATCH_C_LD 0x6000
 548 #define MASK_C_LD  0xe003
 549 #define MATCH_C_SD 0xe000
 550 #define MASK_C_SD  0xe003
 551 #define MATCH_C_ADDIW 0x2001
 552 #define MASK_C_ADDIW  0xe003
 553 #define MATCH_C_LDSP 0x6002
 554 #define MASK_C_LDSP  0xe003
 555 #define MATCH_C_SDSP 0xe002
 556 #define MASK_C_SDSP  0xe003
 557 #define MATCH_C_ADDI4SPN 0x0
 558 #define MASK_C_ADDI4SPN  0xe003
 559 #define MATCH_C_FLD 0x2000
 560 #define MASK_C_FLD  0xe003
 561 #define MATCH_C_LW 0x4000
 562 #define MASK_C_LW  0xe003
 563 #define MATCH_C_FLW 0x6000
 564 #define MASK_C_FLW  0xe003
 565 #define MATCH_C_FSD 0xa000
 566 #define MASK_C_FSD  0xe003
 567 #define MATCH_C_SW 0xc000
 568 #define MASK_C_SW  0xe003
 569 #define MATCH_C_FSW 0xe000
 570 #define MASK_C_FSW  0xe003
 571 #define MATCH_C_ADDI 0x1
 572 #define MASK_C_ADDI  0xe003
 573 #define MATCH_C_JAL 0x2001
 574 #define MASK_C_JAL  0xe003
 575 #define MATCH_C_LI 0x4001
 576 #define MASK_C_LI  0xe003
 577 #define MATCH_C_LUI 0x6001
 578 #define MASK_C_LUI  0xe003
 579 #define MATCH_C_SRLI 0x8001
 580 #define MASK_C_SRLI  0xec03
 581 #define MATCH_C_SRAI 0x8401
 582 #define MASK_C_SRAI  0xec03
 583 #define MATCH_C_ANDI 0x8801
 584 #define MASK_C_ANDI  0xec03
 585 #define MATCH_C_SUB 0x8c01
 586 #define MASK_C_SUB  0xfc63
 587 #define MATCH_C_XOR 0x8c21
 588 #define MASK_C_XOR  0xfc63
 589 #define MATCH_C_OR 0x8c41
 590 #define MASK_C_OR  0xfc63
 591 #define MATCH_C_AND 0x8c61
 592 #define MASK_C_AND  0xfc63
 593 #define MATCH_C_SUBW 0x9c01
 594 #define MASK_C_SUBW  0xfc63
 595 #define MATCH_C_ADDW 0x9c21
 596 #define MASK_C_ADDW  0xfc63
 597 #define MATCH_C_J 0xa001
 598 #define MASK_C_J  0xe003
 599 #define MATCH_C_BEQZ 0xc001
 600 #define MASK_C_BEQZ  0xe003
 601 #define MATCH_C_BNEZ 0xe001
 602 #define MASK_C_BNEZ  0xe003
 603 #define MATCH_C_SLLI 0x2
 604 #define MASK_C_SLLI  0xe003
 605 #define MATCH_C_FLDSP 0x2002
 606 #define MASK_C_FLDSP  0xe003
 607 #define MATCH_C_LWSP 0x4002
 608 #define MASK_C_LWSP  0xe003
 609 #define MATCH_C_FLWSP 0x6002
 610 #define MASK_C_FLWSP  0xe003
 611 #define MATCH_C_MV 0x8002
 612 #define MASK_C_MV  0xf003
 613 #define MATCH_C_ADD 0x9002
 614 #define MASK_C_ADD  0xf003
 615 #define MATCH_C_FSDSP 0xa002
 616 #define MASK_C_FSDSP  0xe003
 617 #define MATCH_C_SWSP 0xc002
 618 #define MASK_C_SWSP  0xe003
 619 #define MATCH_C_FSWSP 0xe002
 620 #define MASK_C_FSWSP  0xe003
 621 #define MATCH_CUSTOM0 0xb
 622 #define MASK_CUSTOM0  0x707f
 623 #define MATCH_CUSTOM0_RS1 0x200b
 624 #define MASK_CUSTOM0_RS1  0x707f
 625 #define MATCH_CUSTOM0_RS1_RS2 0x300b
 626 #define MASK_CUSTOM0_RS1_RS2  0x707f
 627 #define MATCH_CUSTOM0_RD 0x400b
 628 #define MASK_CUSTOM0_RD  0x707f
 629 #define MATCH_CUSTOM0_RD_RS1 0x600b
 630 #define MASK_CUSTOM0_RD_RS1  0x707f
 631 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
 632 #define MASK_CUSTOM0_RD_RS1_RS2  0x707f
 633 #define MATCH_CUSTOM1 0x2b
 634 #define MASK_CUSTOM1  0x707f
 635 #define MATCH_CUSTOM1_RS1 0x202b
 636 #define MASK_CUSTOM1_RS1  0x707f
 637 #define MATCH_CUSTOM1_RS1_RS2 0x302b
 638 #define MASK_CUSTOM1_RS1_RS2  0x707f
 639 #define MATCH_CUSTOM1_RD 0x402b
 640 #define MASK_CUSTOM1_RD  0x707f
 641 #define MATCH_CUSTOM1_RD_RS1 0x602b
 642 #define MASK_CUSTOM1_RD_RS1  0x707f
 643 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
 644 #define MASK_CUSTOM1_RD_RS1_RS2  0x707f
 645 #define MATCH_CUSTOM2 0x5b
 646 #define MASK_CUSTOM2  0x707f
 647 #define MATCH_CUSTOM2_RS1 0x205b
 648 #define MASK_CUSTOM2_RS1  0x707f
 649 #define MATCH_CUSTOM2_RS1_RS2 0x305b
 650 #define MASK_CUSTOM2_RS1_RS2  0x707f
 651 #define MATCH_CUSTOM2_RD 0x405b
 652 #define MASK_CUSTOM2_RD  0x707f
 653 #define MATCH_CUSTOM2_RD_RS1 0x605b
 654 #define MASK_CUSTOM2_RD_RS1  0x707f
 655 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
 656 #define MASK_CUSTOM2_RD_RS1_RS2  0x707f
 657 #define MATCH_CUSTOM3 0x7b
 658 #define MASK_CUSTOM3  0x707f
 659 #define MATCH_CUSTOM3_RS1 0x207b
 660 #define MASK_CUSTOM3_RS1  0x707f
 661 #define MATCH_CUSTOM3_RS1_RS2 0x307b
 662 #define MASK_CUSTOM3_RS1_RS2  0x707f
 663 #define MATCH_CUSTOM3_RD 0x407b
 664 #define MASK_CUSTOM3_RD  0x707f
 665 #define MATCH_CUSTOM3_RD_RS1 0x607b
 666 #define MASK_CUSTOM3_RD_RS1  0x707f
 667 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
 668 #define MASK_CUSTOM3_RD_RS1_RS2  0x707f
 669 #define CSR_FFLAGS 0x1
 670 #define CSR_FRM 0x2
 671 #define CSR_FCSR 0x3
 672 #define CSR_CYCLE 0xc00
 673 #define CSR_TIME 0xc01
 674 #define CSR_INSTRET 0xc02
 675 #define CSR_SSTATUS 0x100
 676 #define CSR_SIE 0x104
 677 #define CSR_STVEC 0x105
 678 #define CSR_SSCRATCH 0x140
 679 #define CSR_SEPC 0x141
 680 #define CSR_SCAUSE 0x142
 681 #define CSR_SBADADDR 0x143
 682 #define CSR_SIP 0x144
 683 #define CSR_SPTBR 0x180
 684 #define CSR_SCYCLE 0xd00
 685 #define CSR_STIME 0xd01
 686 #define CSR_SINSTRET 0xd02
 687 #define CSR_MSTATUS 0x300
 688 #define CSR_MEDELEG 0x302
 689 #define CSR_MIDELEG 0x303
 690 #define CSR_MIE 0x304
 691 #define CSR_MTVEC 0x305
 692 #define CSR_MSCRATCH 0x340
 693 #define CSR_MEPC 0x341
 694 #define CSR_MCAUSE 0x342
 695 #define CSR_MBADADDR 0x343
 696 #define CSR_MIP 0x344
 697 #define CSR_MUCOUNTEREN 0x310
 698 #define CSR_MSCOUNTEREN 0x311
 699 #define CSR_MUCYCLE_DELTA 0x700
 700 #define CSR_MUTIME_DELTA 0x701
 701 #define CSR_MUINSTRET_DELTA 0x702
 702 #define CSR_MSCYCLE_DELTA 0x704
 703 #define CSR_MSTIME_DELTA 0x705
 704 #define CSR_MSINSTRET_DELTA 0x706
 705 #define CSR_TSELECT 0x7a0
 706 #define CSR_TDATA0 0x7a1
 707 #define CSR_TDATA1 0x7a2
 708 #define CSR_TDATA2 0x7a3
 709 #define CSR_DCSR 0x7b0
 710 #define CSR_DPC 0x7b1
 711 #define CSR_DSCRATCH 0x7b2
 712 #define CSR_MCYCLE 0xf00
 713 #define CSR_MTIME 0xf01
 714 #define CSR_MINSTRET 0xf02
 715 #define CSR_MISA 0xf10
 716 #define CSR_MVENDORID 0xf11
 717 #define CSR_MARCHID 0xf12
 718 #define CSR_MIMPID 0xf13
 719 #define CSR_MHARTID 0xf14
 720 #define CSR_MRESET 0x7c2
 721 #define CSR_CYCLEH 0xc80
 722 #define CSR_TIMEH 0xc81
 723 #define CSR_INSTRETH 0xc82
 724 #define CSR_MUCYCLE_DELTAH 0x780
 725 #define CSR_MUTIME_DELTAH 0x781
 726 #define CSR_MUINSTRET_DELTAH 0x782
 727 #define CSR_MSCYCLE_DELTAH 0x784
 728 #define CSR_MSTIME_DELTAH 0x785
 729 #define CSR_MSINSTRET_DELTAH 0x786
 730 #define CSR_MCYCLEH 0xf80
 731 #define CSR_MTIMEH 0xf81
 732 #define CSR_MINSTRETH 0xf82
 733 #define CAUSE_MISALIGNED_FETCH 0x0
 734 #define CAUSE_FAULT_FETCH 0x1
 735 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
 736 #define CAUSE_BREAKPOINT 0x3
 737 #define CAUSE_MISALIGNED_LOAD 0x4
 738 #define CAUSE_FAULT_LOAD 0x5
 739 #define CAUSE_MISALIGNED_STORE 0x6
 740 #define CAUSE_FAULT_STORE 0x7
 741 #define CAUSE_USER_ECALL 0x8
 742 #define CAUSE_SUPERVISOR_ECALL 0x9
 743 #define CAUSE_HYPERVISOR_ECALL 0xa
 744 #define CAUSE_MACHINE_ECALL 0xb
 745 #endif
 746 #ifdef DECLARE_INSN
 747 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
 748 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
 749 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
 750 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
 751 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
 752 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
 753 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
 754 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
 755 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
 756 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
 757 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
 758 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
 759 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
 760 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
 761 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
 762 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
 763 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
 764 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
 765 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
 766 DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
 767 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
 768 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
 769 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
 770 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
 771 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
 772 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
 773 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
 774 DECLARE_INSN(or, MATCH_OR, MASK_OR)
 775 DECLARE_INSN(and, MATCH_AND, MASK_AND)
 776 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
 777 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
 778 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
 779 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
 780 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
 781 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
 782 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
 783 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
 784 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
 785 DECLARE_INSN(lb, MATCH_LB, MASK_LB)
 786 DECLARE_INSN(lh, MATCH_LH, MASK_LH)
 787 DECLARE_INSN(lw, MATCH_LW, MASK_LW)
 788 DECLARE_INSN(ld, MATCH_LD, MASK_LD)
 789 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
 790 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
 791 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
 792 DECLARE_INSN(sb, MATCH_SB, MASK_SB)
 793 DECLARE_INSN(sh, MATCH_SH, MASK_SH)
 794 DECLARE_INSN(sw, MATCH_SW, MASK_SW)
 795 DECLARE_INSN(sd, MATCH_SD, MASK_SD)
 796 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
 797 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
 798 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
 799 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
 800 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
 801 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
 802 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
 803 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
 804 DECLARE_INSN(rem, MATCH_REM, MASK_REM)
 805 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
 806 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
 807 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
 808 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
 809 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
 810 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
 811 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
 812 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
 813 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
 814 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
 815 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
 816 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
 817 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
 818 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
 819 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
 820 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
 821 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
 822 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
 823 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
 824 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
 825 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
 826 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
 827 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
 828 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
 829 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
 830 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
 831 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
 832 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
 833 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
 834 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
 835 DECLARE_INSN(uret, MATCH_URET, MASK_URET)
 836 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
 837 DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
 838 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
 839 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
 840 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
 841 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
 842 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
 843 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
 844 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
 845 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
 846 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
 847 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
 848 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
 849 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
 850 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
 851 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
 852 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
 853 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
 854 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
 855 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
 856 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
 857 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
 858 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
 859 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
 860 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
 861 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
 862 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
 863 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
 864 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
 865 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
 866 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
 867 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
 868 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
 869 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
 870 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
 871 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
 872 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
 873 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
 874 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
 875 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
 876 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
 877 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
 878 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
 879 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
 880 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
 881 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
 882 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
 883 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
 884 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
 885 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
 886 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
 887 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
 888 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
 889 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
 890 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
 891 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
 892 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
 893 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
 894 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
 895 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
 896 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
 897 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
 898 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
 899 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
 900 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
 901 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
 902 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
 903 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
 904 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
 905 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
 906 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
 907 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
 908 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
 909 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
 910 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
 911 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
 912 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
 913 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
 914 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
 915 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
 916 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
 917 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
 918 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
 919 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
 920 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
 921 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
 922 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
 923 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
 924 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
 925 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
 926 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
 927 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
 928 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
 929 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
 930 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
 931 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
 932 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
 933 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
 934 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
 935 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
 936 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
 937 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
 938 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
 939 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
 940 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
 941 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
 942 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
 943 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
 944 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
 945 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
 946 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
 947 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
 948 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
 949 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
 950 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
 951 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
 952 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
 953 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
 954 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
 955 DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
 956 DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
 957 DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
 958 DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
 959 DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
 960 DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
 961 DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
 962 DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
 963 DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
 964 DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
 965 DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
 966 DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
 967 DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
 968 DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
 969 DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
 970 DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
 971 DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
 972 DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
 973 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
 974 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
 975 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
 976 #endif
 977 #ifdef DECLARE_CSR
 978 DECLARE_CSR(fflags, CSR_FFLAGS)
 979 DECLARE_CSR(frm, CSR_FRM)
 980 DECLARE_CSR(fcsr, CSR_FCSR)
 981 DECLARE_CSR(cycle, CSR_CYCLE)
 982 DECLARE_CSR(time, CSR_TIME)
 983 DECLARE_CSR(instret, CSR_INSTRET)
 984 DECLARE_CSR(sstatus, CSR_SSTATUS)
 985 DECLARE_CSR(sie, CSR_SIE)
 986 DECLARE_CSR(stvec, CSR_STVEC)
 987 DECLARE_CSR(sscratch, CSR_SSCRATCH)
 988 DECLARE_CSR(sepc, CSR_SEPC)
 989 DECLARE_CSR(scause, CSR_SCAUSE)
 990 DECLARE_CSR(sbadaddr, CSR_SBADADDR)
 991 DECLARE_CSR(sip, CSR_SIP)
 992 DECLARE_CSR(sptbr, CSR_SPTBR)
 993 DECLARE_CSR(scycle, CSR_SCYCLE)
 994 DECLARE_CSR(stime, CSR_STIME)
 995 DECLARE_CSR(sinstret, CSR_SINSTRET)
 996 DECLARE_CSR(mstatus, CSR_MSTATUS)
 997 DECLARE_CSR(medeleg, CSR_MEDELEG)
 998 DECLARE_CSR(mideleg, CSR_MIDELEG)
 999 DECLARE_CSR(mie, CSR_MIE)
1000 DECLARE_CSR(mtvec, CSR_MTVEC)
1001 DECLARE_CSR(mscratch, CSR_MSCRATCH)
1002 DECLARE_CSR(mepc, CSR_MEPC)
1003 DECLARE_CSR(mcause, CSR_MCAUSE)
1004 DECLARE_CSR(mbadaddr, CSR_MBADADDR)
1005 DECLARE_CSR(mip, CSR_MIP)
1006 DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
1007 DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
1008 DECLARE_CSR(mucycle_delta, CSR_MUCYCLE_DELTA)
1009 DECLARE_CSR(mutime_delta, CSR_MUTIME_DELTA)
1010 DECLARE_CSR(muinstret_delta, CSR_MUINSTRET_DELTA)
1011 DECLARE_CSR(mscycle_delta, CSR_MSCYCLE_DELTA)
1012 DECLARE_CSR(mstime_delta, CSR_MSTIME_DELTA)
1013 DECLARE_CSR(msinstret_delta, CSR_MSINSTRET_DELTA)
1014 DECLARE_CSR(tselect, CSR_TSELECT)
1015 DECLARE_CSR(tdata0, CSR_TDATA0)
1016 DECLARE_CSR(tdata1, CSR_TDATA1)
1017 DECLARE_CSR(tdata2, CSR_TDATA2)
1018 DECLARE_CSR(dcsr, CSR_DCSR)
1019 DECLARE_CSR(dpc, CSR_DPC)
1020 DECLARE_CSR(dscratch, CSR_DSCRATCH)
1021 DECLARE_CSR(mcycle, CSR_MCYCLE)
1022 DECLARE_CSR(mtime, CSR_MTIME)
1023 DECLARE_CSR(minstret, CSR_MINSTRET)
1024 DECLARE_CSR(misa, CSR_MISA)
1025 DECLARE_CSR(mvendorid, CSR_MVENDORID)
1026 DECLARE_CSR(marchid, CSR_MARCHID)
1027 DECLARE_CSR(mimpid, CSR_MIMPID)
1028 DECLARE_CSR(mhartid, CSR_MHARTID)
1029 DECLARE_CSR(mreset, CSR_MRESET)
1030 DECLARE_CSR(cycleh, CSR_CYCLEH)
1031 DECLARE_CSR(timeh, CSR_TIMEH)
1032 DECLARE_CSR(instreth, CSR_INSTRETH)
1033 DECLARE_CSR(mucycle_deltah, CSR_MUCYCLE_DELTAH)
1034 DECLARE_CSR(mutime_deltah, CSR_MUTIME_DELTAH)
1035 DECLARE_CSR(muinstret_deltah, CSR_MUINSTRET_DELTAH)
1036 DECLARE_CSR(mscycle_deltah, CSR_MSCYCLE_DELTAH)
1037 DECLARE_CSR(mstime_deltah, CSR_MSTIME_DELTAH)
1038 DECLARE_CSR(msinstret_deltah, CSR_MSINSTRET_DELTAH)
1039 DECLARE_CSR(mcycleh, CSR_MCYCLEH)
1040 DECLARE_CSR(mtimeh, CSR_MTIMEH)
1041 DECLARE_CSR(minstreth, CSR_MINSTRETH)
1042 #endif
1043 #ifdef DECLARE_CAUSE
1044 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
1045 DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
1046 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
1047 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
1048 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
1049 DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
1050 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
1051 DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
1052 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
1053 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
1054 DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
1055 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
1056 #endif