riscv/execute.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "mmu.h"
   5 #include "sim.h"
   6 #include <cassert>
   7
   8
   9 static void commit_log_stash_privilege(state_t* state)
  10 {
  11 #ifdef RISCV_ENABLE_COMMITLOG
  12   state->last_inst_priv = state->prv;
  13 #endif
  14 }
  15
  16 static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
  17 {
  18 #ifdef RISCV_ENABLE_COMMITLOG
  19   int32_t priv = state->last_inst_priv;
  20   uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
  21   if (state->log_reg_write.addr) {
  22     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
  23             priv,
  24             pc,
  25             insn.bits() & mask,
  26             state->log_reg_write.addr & 1 ? 'f' : 'x',
  27             state->log_reg_write.addr >> 1,
  28             state->log_reg_write.data);
  29   } else {
  30     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ")\n", priv, pc, insn.bits() & mask);
  31   }
  32   state->log_reg_write.addr = 0;
  33 #endif
  34 }
  35
  36 inline void processor_t::update_histogram(reg_t pc)
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   pc_histogram[pc]++;
  40 #endif
  41 }
  42
  43 // This is expected to be inlined by the compiler so each use of execute_insn
  44 // includes a duplicated body of the function to get separate fetch.func
  45 // function calls.
  46 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
  47 {
  48   commit_log_stash_privilege(p->get_state());
  49   reg_t npc = fetch.func(p, fetch.insn, pc);
  50   if (!invalid_pc(npc)) {
  51     commit_log_print_insn(p->get_state(), pc, fetch.insn);
  52     p->update_histogram(pc);
  53   }
  54   return npc;
  55 }
  56
  57 bool processor_t::slow_path()
  58 {
  59   return debug || state.single_step != state.STEP_NONE || state.dcsr.cause;
  60 }
  61
  62 // fetch/decode/execute loop
  63 void processor_t::step(size_t n)
  64 {
  65   if (state.dcsr.cause == DCSR_CAUSE_NONE) {
  66     if (halt_request) {
  67       enter_debug_mode(DCSR_CAUSE_DEBUGINT);
  68     } // !!!The halt bit in DCSR is deprecated.
  69     else if (state.dcsr.halt) {
  70       enter_debug_mode(DCSR_CAUSE_HALT);
  71     }
  72   }
  73
  74   while (n > 0) {
  75     size_t instret = 0;
  76     reg_t pc = state.pc;
  77     mmu_t* _mmu = mmu;
  78
  79     #define advance_pc() \
  80      if (unlikely(invalid_pc(pc))) { \
  81        switch (pc) { \
  82          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
  83          case PC_SERIALIZE_AFTER: n = ++instret; break; \
  84          default: abort(); \
  85        } \
  86        pc = state.pc; \
  87        break; \
  88      } else { \
  89        state.pc = pc; \
  90        instret++; \
  91      }
  92
  93     try
  94     {
  95       take_pending_interrupt();
  96
  97       if (unlikely(slow_path()))
  98       {
  99         while (instret < n)
 100         {
 101           if (unlikely(state.single_step == state.STEP_STEPPING)) {
 102             state.single_step = state.STEP_STEPPED;
 103           }
 104
 105           insn_fetch_t fetch = mmu->load_insn(pc);
 106           if (debug && !state.serialized)
 107             disasm(fetch.insn);
 108           pc = execute_insn(this, pc, fetch);
 109           bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
 110
 111           advance_pc();
 112
 113           if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
 114             state.single_step = state.STEP_NONE;
 115             enter_debug_mode(DCSR_CAUSE_STEP);
 116             // enter_debug_mode changed state.pc, so we can't just continue.
 117             break;
 118           }
 119
 120           if (unlikely(state.pc >= DEBUG_START &&
 121                        state.pc < DEBUG_END)) {
 122             // We're waiting for the debugger to tell us something.
 123             return;
 124           }
 125
 126
 127
 128         }
 129       }
 130       else while (instret < n)
 131       {
 132         // This code uses a modified Duff's Device to improve the performance
 133         // of executing instructions. While typical Duff's Devices are used
 134         // for software pipelining, the switch statement below primarily
 135         // benefits from separate call points for the fetch.func function call
 136         // found in each execute_insn. This function call is an indirect jump
 137         // that depends on the current instruction. By having an indirect jump
 138         // dedicated for each icache entry, you improve the performance of the
 139         // host's next address predictor. Each case in the switch statement
 140         // allows for the program flow to contine to the next case if it
 141         // corresponds to the next instruction in the program and instret is
 142         // still less than n.
 143         //
 144         // According to Andrew Waterman's recollection, this optimization
 145         // resulted in approximately a 2x performance increase.
 146         //
 147         // If there is support for compressed instructions, the mmu and the
 148         // switch statement get more complicated. Each branch target is stored
 149         // in the index corresponding to mmu->icache_index(), but consecutive
 150         // non-branching instructions are stored in consecutive indices even if
 151         // mmu->icache_index() specifies a different index (which is the case
 152         // for 32-bit instructions in the presence of compressed instructions).
 153
 154         // This figures out where to jump to in the switch statement
 155         size_t idx = _mmu->icache_index(pc);
 156
 157         // This gets the cached decoded instruction from the MMU. If the MMU
 158         // does not have the current pc cached, it will refill the MMU and
 159         // return the correct entry. ic_entry->data.func is the C++ function
 160         // corresponding to the instruction.
 161         auto ic_entry = _mmu->access_icache(pc);
 162
 163         // This macro is included in "icache.h" included within the switch
 164         // statement below. The indirect jump corresponding to the instruction
 165         // is located within the execute_insn() function call.
 166         #define ICACHE_ACCESS(i) { \
 167           insn_fetch_t fetch = ic_entry->data; \
 168           ic_entry++; \
 169           pc = execute_insn(this, pc, fetch); \
 170           if (i == mmu_t::ICACHE_ENTRIES-1) break; \
 171           if (unlikely(ic_entry->tag != pc)) goto miss; \
 172           if (unlikely(instret+1 == n)) break; \
 173           instret++; \
 174           state.pc = pc; \
 175         }
 176
 177         // This switch statement implements the modified Duff's device as
 178         // explained above.
 179         switch (idx) {
 180           // "icache.h" is generated by the gen_icache script
 181           #include "icache.h"
 182         }
 183
 184         advance_pc();
 185         continue;
 186
 187 miss:
 188         advance_pc();
 189         // refill I$ if it looks like there wasn't a taken branch
 190         if (pc > (ic_entry-1)->tag && pc <= (ic_entry-1)->tag + MAX_INSN_LENGTH)
 191           _mmu->refill_icache(pc, ic_entry);
 192       }
 193     }
 194     catch(trap_t& t)
 195     {
 196       take_trap(t, pc);
 197       n = instret;
 198
 199       if (unlikely(state.single_step == state.STEP_STEPPED)) {
 200         state.single_step = state.STEP_NONE;
 201         enter_debug_mode(DCSR_CAUSE_STEP);
 202       }
 203     }
 204     catch (trigger_matched_t& t)
 205     {
 206       if (mmu->matched_trigger) {
 207         // This exception came from the MMU. That means the instruction hasn't
 208         // fully executed yet. We start it again, but this time it won't throw
 209         // an exception because matched_trigger is already set. (All memory
 210         // instructions are idempotent so restarting is safe.)
 211
 212         insn_fetch_t fetch = mmu->load_insn(pc);
 213         pc = execute_insn(this, pc, fetch);
 214         advance_pc();
 215
 216         delete mmu->matched_trigger;
 217         mmu->matched_trigger = NULL;
 218       }
 219       switch (state.mcontrol[t.index].action) {
 220         case ACTION_DEBUG_MODE:
 221           enter_debug_mode(DCSR_CAUSE_HWBP);
 222           break;
 223         case ACTION_DEBUG_EXCEPTION: {
 224           mem_trap_t trap(CAUSE_BREAKPOINT, t.address);
 225           take_trap(trap, pc);
 226           break;
 227         }
 228         default:
 229           abort();
 230       }
 231     }
 232
 233     state.minstret += instret;
 234     n -= instret;
 235   }
 236 }