riscv/execute.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "mmu.h"
   5 #include "sim.h"
   6 #include <cassert>
   7
   8
   9 static void commit_log_stash_privilege(state_t* state)
  10 {
  11 #ifdef RISCV_ENABLE_COMMITLOG
  12   state->last_inst_priv = state->prv;
  13 #endif
  14 }
  15
  16 static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
  17 {
  18 #ifdef RISCV_ENABLE_COMMITLOG
  19   int32_t priv = state->last_inst_priv;
  20   uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
  21   if (state->log_reg_write.addr) {
  22     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
  23             priv,
  24             pc,
  25             insn.bits() & mask,
  26             state->log_reg_write.addr & 1 ? 'f' : 'x',
  27             state->log_reg_write.addr >> 1,
  28             state->log_reg_write.data);
  29   } else {
  30     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ")\n", priv, pc, insn.bits() & mask);
  31   }
  32   state->log_reg_write.addr = 0;
  33 #endif
  34 }
  35
  36 inline void processor_t::update_histogram(reg_t pc)
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   pc_histogram[pc]++;
  40 #endif
  41 }
  42
  43 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
  44 {
  45   commit_log_stash_privilege(p->get_state());
  46   reg_t npc = fetch.func(p, fetch.insn, pc);
  47   if (!invalid_pc(npc)) {
  48     commit_log_print_insn(p->get_state(), pc, fetch.insn);
  49     p->update_histogram(pc);
  50   }
  51   return npc;
  52 }
  53
  54 bool processor_t::slow_path()
  55 {
  56   return debug || state.single_step != state.STEP_NONE || state.dcsr.cause;
  57 }
  58
  59 // fetch/decode/execute loop
  60 void processor_t::step(size_t n)
  61 {
  62   if (state.dcsr.cause == DCSR_CAUSE_NONE) {
  63     // TODO: get_interrupt() isn't super fast. Does that matter?
  64     if (sim->debug_module.get_interrupt(id)) {
  65       enter_debug_mode(DCSR_CAUSE_DEBUGINT);
  66     } else if (state.dcsr.halt) {
  67       enter_debug_mode(DCSR_CAUSE_HALT);
  68     }
  69   } else {
  70     // In Debug Mode, just do 11 steps at a time. Otherwise we're going to be
  71     // spinning the rest of the time anyway.
  72     n = std::min(n, (size_t) 11);
  73   }
  74
  75   while (n > 0) {
  76     size_t instret = 0;
  77     reg_t pc = state.pc;
  78     mmu_t* _mmu = mmu;
  79
  80     #define advance_pc() \
  81      if (unlikely(invalid_pc(pc))) { \
  82        switch (pc) { \
  83          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
  84          case PC_SERIALIZE_AFTER: instret++; break; \
  85          default: abort(); \
  86        } \
  87        pc = state.pc; \
  88        break; \
  89      } else { \
  90        state.pc = pc; \
  91        instret++; \
  92      }
  93
  94     try
  95     {
  96       take_interrupt();
  97
  98       if (unlikely(slow_path()))
  99       {
 100         while (instret < n)
 101         {
 102           if (unlikely(state.single_step == state.STEP_STEPPING)) {
 103             state.single_step = state.STEP_STEPPED;
 104           }
 105
 106           insn_fetch_t fetch = mmu->load_insn(pc);
 107           if (debug && !state.serialized)
 108             disasm(fetch.insn);
 109           pc = execute_insn(this, pc, fetch);
 110           bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
 111
 112           advance_pc();
 113
 114           if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
 115             state.single_step = state.STEP_NONE;
 116             enter_debug_mode(DCSR_CAUSE_STEP);
 117             // enter_debug_mode changed state.pc, so we can't just continue.
 118             break;
 119           }
 120         }
 121       }
 122       else while (instret < n)
 123       {
 124         size_t idx = _mmu->icache_index(pc);
 125         auto ic_entry = _mmu->access_icache(pc);
 126
 127         #define ICACHE_ACCESS(i) { \
 128           insn_fetch_t fetch = ic_entry->data; \
 129           ic_entry++; \
 130           pc = execute_insn(this, pc, fetch); \
 131           if (i == mmu_t::ICACHE_ENTRIES-1) break; \
 132           if (unlikely(ic_entry->tag != pc)) goto miss; \
 133           if (unlikely(instret+1 == n)) break; \
 134           instret++; \
 135           state.pc = pc; \
 136         }
 137
 138         switch (idx) {
 139           #include "icache.h"
 140         }
 141
 142         advance_pc();
 143         continue;
 144
 145 miss:
 146         advance_pc();
 147         // refill I$ if it looks like there wasn't a taken branch
 148         if (pc > (ic_entry-1)->tag && pc <= (ic_entry-1)->tag + MAX_INSN_LENGTH)
 149           _mmu->refill_icache(pc, ic_entry);
 150       }
 151     }
 152     catch(trap_t& t)
 153     {
 154       take_trap(t, pc);
 155       n = instret;
 156     }
 157     catch (trigger_matched_t& t)
 158     {
 159       if (mmu->matched_trigger) {
 160         // This exception came from the MMU. That means the instruction hasn't
 161         // fully executed yet. We start it again, but this time it won't throw
 162         // an exception because matched_trigger is already set. (All memory
 163         // instructions are idempotent so restarting is safe.)
 164
 165         insn_fetch_t fetch = mmu->load_insn(pc);
 166         pc = execute_insn(this, pc, fetch);
 167         advance_pc();
 168
 169         delete mmu->matched_trigger;
 170         mmu->matched_trigger = NULL;
 171       }
 172       switch (state.mcontrol[t.index].action) {
 173         case ACTION_DEBUG_MODE:
 174           enter_debug_mode(DCSR_CAUSE_HWBP);
 175           break;
 176         case ACTION_DEBUG_EXCEPTION: {
 177           mem_trap_t trap(CAUSE_BREAKPOINT, t.address);
 178           take_trap(trap, pc);
 179           break;
 180         }
 181         default:
 182           abort();
 183       }
 184     }
 185
 186     state.minstret += instret;
 187     n -= instret;
 188   }
 189 }