riscv/execute.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "mmu.h"
   5 #include "sim.h"
   6 #include <cassert>
   7
   8
   9 static void commit_log_stash_privilege(state_t* state)
  10 {
  11 #ifdef RISCV_ENABLE_COMMITLOG
  12   state->last_inst_priv = state->prv;
  13 #endif
  14 }
  15
  16 static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
  17 {
  18 #ifdef RISCV_ENABLE_COMMITLOG
  19   int32_t priv = state->last_inst_priv;
  20   uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
  21   if (state->log_reg_write.addr) {
  22     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
  23             priv,
  24             pc,
  25             insn.bits() & mask,
  26             state->log_reg_write.addr & 1 ? 'f' : 'x',
  27             state->log_reg_write.addr >> 1,
  28             state->log_reg_write.data);
  29   } else {
  30     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ")\n", priv, pc, insn.bits() & mask);
  31   }
  32   state->log_reg_write.addr = 0;
  33 #endif
  34 }
  35
  36 inline void processor_t::update_histogram(reg_t pc)
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   pc_histogram[pc]++;
  40 #endif
  41 }
  42
  43 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
  44 {
  45   commit_log_stash_privilege(p->get_state());
  46   reg_t npc = fetch.func(p, fetch.insn, pc);
  47   if (!invalid_pc(npc)) {
  48     commit_log_print_insn(p->get_state(), pc, fetch.insn);
  49     p->update_histogram(pc);
  50   }
  51   return npc;
  52 }
  53
  54 void processor_t::update_slow_path()
  55 {
  56   slow_path = debug || state.single_step != state.STEP_NONE || state.dcsr.cause;
  57   if (slow_path)
  58     return;
  59 }
  60
  61 // fetch/decode/execute loop
  62 void processor_t::step(size_t n)
  63 {
  64   if (state.dcsr.cause == DCSR_CAUSE_NONE) {
  65     // TODO: get_interrupt() isn't super fast. Does that matter?
  66     if (sim->debug_module.get_interrupt(id)) {
  67       enter_debug_mode(DCSR_CAUSE_DEBUGINT);
  68     } else if (state.dcsr.halt) {
  69       enter_debug_mode(DCSR_CAUSE_HALT);
  70     }
  71   } else {
  72     // In Debug Mode, just do 11 steps at a time. Otherwise we're going to be
  73     // spinning the rest of the time anyway.
  74     n = std::min(n, (size_t) 11);
  75   }
  76
  77   while (n > 0) {
  78     size_t instret = 0;
  79     reg_t pc = state.pc;
  80     mmu_t* _mmu = mmu;
  81
  82     #define advance_pc() \
  83      if (unlikely(invalid_pc(pc))) { \
  84        switch (pc) { \
  85          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
  86          case PC_SERIALIZE_AFTER: instret++; break; \
  87          default: abort(); \
  88        } \
  89        pc = state.pc; \
  90        break; \
  91      } else { \
  92        state.pc = pc; \
  93        instret++; \
  94      }
  95
  96     try
  97     {
  98       take_interrupt();
  99
 100       if (unlikely(slow_path))
 101       {
 102         while (instret < n)
 103         {
 104           if (unlikely(state.single_step == state.STEP_STEPPING)) {
 105             state.single_step = state.STEP_STEPPED;
 106           }
 107
 108           insn_fetch_t fetch = mmu->load_insn(pc);
 109           if (debug && !state.serialized)
 110             disasm(fetch.insn);
 111           pc = execute_insn(this, pc, fetch);
 112           bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
 113
 114           advance_pc();
 115
 116           if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
 117             state.single_step = state.STEP_NONE;
 118             enter_debug_mode(DCSR_CAUSE_STEP);
 119             // enter_debug_mode changed state.pc, so we can't just continue.
 120             break;
 121           }
 122         }
 123       }
 124       else while (instret < n)
 125       {
 126         size_t idx = _mmu->icache_index(pc);
 127         auto ic_entry = _mmu->access_icache(pc);
 128
 129         #define ICACHE_ACCESS(i) { \
 130           insn_fetch_t fetch = ic_entry->data; \
 131           ic_entry++; \
 132           pc = execute_insn(this, pc, fetch); \
 133           if (i == mmu_t::ICACHE_ENTRIES-1) break; \
 134           if (unlikely(ic_entry->tag != pc)) goto miss; \
 135           if (unlikely(instret+1 == n)) break; \
 136           instret++; \
 137           state.pc = pc; \
 138         }
 139
 140         switch (idx) {
 141           #include "icache.h"
 142         }
 143
 144         advance_pc();
 145         continue;
 146
 147 miss:
 148         advance_pc();
 149         // refill I$ if it looks like there wasn't a taken branch
 150         if (pc > (ic_entry-1)->tag && pc <= (ic_entry-1)->tag + MAX_INSN_LENGTH)
 151           _mmu->refill_icache(pc, ic_entry);
 152       }
 153     }
 154     catch(trap_t& t)
 155     {
 156       take_trap(t, pc);
 157       n = instret;
 158     }
 159     catch (trigger_matched_t& t)
 160     {
 161       if (mmu->matched_trigger) {
 162         // This exception came from the MMU. That means the instruction hasn't
 163         // fully executed yet. We start it again, but this time it won't throw
 164         // an exception because matched_trigger is already set. (All memory
 165         // instructions are idempotent so restarting is safe.)
 166
 167         insn_fetch_t fetch = mmu->load_insn(pc);
 168         pc = execute_insn(this, pc, fetch);
 169         advance_pc();
 170
 171         delete mmu->matched_trigger;
 172         mmu->matched_trigger = NULL;
 173       }
 174       assert(state.mcontrol[t.index].action != ACTION_NONE);
 175       switch (state.mcontrol[t.index].action) {
 176         case ACTION_DEBUG_MODE:
 177           enter_debug_mode(DCSR_CAUSE_HWBP);
 178           break;
 179         default:
 180           assert(0);
 181       }
 182     }
 183
 184     state.minstret += instret;
 185     n -= instret;
 186   }
 187 }