riscv/execute.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "mmu.h"
   5 #include "sim.h"
   6 #include <cassert>
   7
   8
   9 static void commit_log_stash_privilege(state_t* state)
  10 {
  11 #ifdef RISCV_ENABLE_COMMITLOG
  12   state->last_inst_priv = state->prv;
  13 #endif
  14 }
  15
  16 static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
  17 {
  18 #ifdef RISCV_ENABLE_COMMITLOG
  19   int32_t priv = state->last_inst_priv;
  20   uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
  21   if (state->log_reg_write.addr) {
  22     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
  23             priv,
  24             pc,
  25             insn.bits() & mask,
  26             state->log_reg_write.addr & 1 ? 'f' : 'x',
  27             state->log_reg_write.addr >> 1,
  28             state->log_reg_write.data);
  29   } else {
  30     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ")\n", priv, pc, insn.bits() & mask);
  31   }
  32   state->log_reg_write.addr = 0;
  33 #endif
  34 }
  35
  36 inline void processor_t::update_histogram(reg_t pc)
  37 {
  38 #ifdef RISCV_ENABLE_HISTOGRAM
  39   pc_histogram[pc]++;
  40 #endif
  41 }
  42
  43 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
  44 {
  45   commit_log_stash_privilege(p->get_state());
  46   reg_t npc = fetch.func(p, fetch.insn, pc);
  47   if (!invalid_pc(npc)) {
  48     commit_log_print_insn(p->get_state(), pc, fetch.insn);
  49     p->update_histogram(pc);
  50   }
  51   return npc;
  52 }
  53
  54 // fetch/decode/execute loop
  55 void processor_t::step(size_t n)
  56 {
  57   // TODO: get_interrupt() isn't super fast. Does that matter?
  58   if (state.dcsr.cause == DCSR_CAUSE_NONE &&
  59       sim->debug_module.get_interrupt(id)) {
  60     enter_debug_mode(DCSR_CAUSE_DEBUGINT);
  61   }
  62
  63   if (state.dcsr.cause != DCSR_CAUSE_NONE) {
  64     // In Debug Mode, just do 100 steps at a time. Otherwise we're going to be
  65     // spinning the rest of the time anyway.
  66     n = std::max(n, (size_t) 100);
  67   }
  68
  69   while (n > 0) {
  70     size_t instret = 0;
  71     reg_t pc = state.pc;
  72     mmu_t* _mmu = mmu;
  73
  74     #define advance_pc() \
  75      if (unlikely(invalid_pc(pc))) { \
  76        switch (pc) { \
  77          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
  78          case PC_SERIALIZE_AFTER: instret++; break; \
  79          default: abort(); \
  80        } \
  81        pc = state.pc; \
  82        break; \
  83      } else { \
  84        state.pc = pc; \
  85        instret++; \
  86      }
  87
  88     try
  89     {
  90       take_interrupt();
  91
  92       if (unlikely(debug))
  93       {
  94         while (instret < n)
  95         {
  96           insn_fetch_t fetch = mmu->load_insn(pc);
  97           if (!state.serialized)
  98             disasm(fetch.insn);
  99           pc = execute_insn(this, pc, fetch);
 100           advance_pc();
 101         }
 102       }
 103       else while (instret < n)
 104       {
 105         size_t idx = _mmu->icache_index(pc);
 106         auto ic_entry = _mmu->access_icache(pc);
 107
 108         #define ICACHE_ACCESS(i) { \
 109           insn_fetch_t fetch = ic_entry->data; \
 110           ic_entry++; \
 111           pc = execute_insn(this, pc, fetch); \
 112           if (i == mmu_t::ICACHE_ENTRIES-1) break; \
 113           if (unlikely(ic_entry->tag != pc)) goto miss; \
 114           if (unlikely(instret+1 == n)) break; \
 115           instret++; \
 116           state.pc = pc; \
 117         }
 118
 119         switch (idx) {
 120           #include "icache.h"
 121         }
 122
 123         advance_pc();
 124         continue;
 125
 126 miss:
 127         advance_pc();
 128         // refill I$ if it looks like there wasn't a taken branch
 129         if (pc > (ic_entry-1)->tag && pc <= (ic_entry-1)->tag + MAX_INSN_LENGTH)
 130           _mmu->refill_icache(pc, ic_entry);
 131       }
 132     }
 133     catch(trap_t& t)
 134     {
 135       take_trap(t, pc);
 136       n = instret;
 137     }
 138
 139     state.minstret += instret;
 140     n -= instret;
 141   }
 142 }