Merge pull request #117 from riscv/multicore_debug
[riscv-isa-sim.git] / riscv / insn_template.cc
1 // See LICENSE for license details.
2
3 #include "insn_template.h"
4
5 reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
6 {
7 int xlen = 32;
8 reg_t npc = sext_xlen(pc + insn_length(OPCODE));
9 #include "insns/NAME.h"
10 trace_opcode(p, OPCODE, insn);
11 return npc;
12 }
13
14 reg_t rv64_NAME(processor_t* p, insn_t insn, reg_t pc)
15 {
16 int xlen = 64;
17 reg_t npc = sext_xlen(pc + insn_length(OPCODE));
18 #include "insns/NAME.h"
19 trace_opcode(p, OPCODE, insn);
20 return npc;
21 }