New RV64C proposal
[riscv-isa-sim.git] / riscv / insns / c_addi.h
1 require_extension('C');
2 if (insn.rvc_rd() == 0) { // c.addi16sp
3 WRITE_REG(X_SP, sext_xlen(RVC_SP + insn.rvc_addi16sp_imm()));
4 } else {
5 require(insn.rvc_imm() != 0);
6 WRITE_RD(sext_xlen(RVC_RS1 + insn.rvc_imm()));
7 }