New RV64C proposal

[riscv-isa-sim.git] / riscv / insns / c_addw.h

require_extension('C');
require_rv64;
require(insn.rvc_rd() != 0 && insn.rvc_rs2() != 0);
WRITE_RD(sext32(RVC_RS1 + RVC_RS2));