work towards rvc 1.8
[riscv-isa-sim.git] / riscv / insns / c_jal.h
1 require_extension('C');
2 if (xlen == 32) {
3 reg_t tmp = npc;
4 set_pc(pc + insn.rvc_j_imm());
5 WRITE_REG(X_RA, tmp);
6 } else {
7 WRITE_RD(sext32(RVC_RS1 + insn.rvc_imm()));
8 }