New RV64C proposal
[riscv-isa-sim.git] / riscv / insns / c_lui.h
1 require_extension('C');
2 require(insn.rvc_rd() != 0);
3 if (insn.rvc_imm() == 0) { // c.jalr
4 reg_t tmp = npc;
5 set_pc(RVC_RS1 & ~reg_t(1));
6 WRITE_REG(X_RA, tmp);
7 } else {
8 WRITE_RD(insn.rvc_imm() << 12);
9 }