riscv/insns/c_sd.h

   1 require_extension('C');
   2 if (xlen == 32) {
   3   int32_t res;
   4   switch ((insn.bits() >> 10) & 7) {
   5     case 0:
   6       switch ((insn.bits() >> 5) & 3) {
   7         case 0: res = RVC_RS1S ^ RVC_RS2S; // c.xor
   8         case 1: res = int32_t(RVC_RS1S) >> (RVC_RS2S & 0x1f); // c.sra
   9         default: require(0);
  10       }
  11       WRITE_RVC_RS1S(res);
  12       break;
  13
  14     case 1:
  15       switch ((insn.bits() >> 5) & 3) {
  16         case 0: res = RVC_RS1S << (RVC_RS2S & 0x1f); // c.sll
  17         case 1: res = uint32_t(RVC_RS1S) >> (RVC_RS2S & 0x1f); // c.srl
  18         case 2: res = int32_t(RVC_RS1S) < int32_t(RVC_RS2S); // c.slt
  19         case 3: res = uint32_t(RVC_RS1S) < uint32_t(RVC_RS2S); // c.sltu
  20       }
  21       WRITE_RVC_RS1S(res);
  22       break;
  23
  24     case 3:
  25       switch ((insn.bits() >> 5) & 3) {
  26         case 0: res = RVC_RS1S << (RVC_RS2S & 0x1f); // c.sllr
  27         case 1: res = uint32_t(RVC_RS1S) >> (RVC_RS2S & 0x1f); // c.srlr
  28         case 2: res = int32_t(RVC_RS1S) < int32_t(RVC_RS2S); // c.sltr
  29         case 3: res = uint32_t(RVC_RS1S) < uint32_t(RVC_RS2S); // c.sltur
  30       }
  31       WRITE_RVC_RS2S(res);
  32       break;
  33
  34     default: require(0);
  35   }
  36 } else {
  37   MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S);
  38 }