Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded...

[riscv-isa-sim.git] / riscv / insns / c_slli.h

require_extension('C');
require(insn.rvc_zimm() < xlen && insn.rvc_zimm() > 0);
WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_zimm()));