riscv/insns/c_slliw.h

   1 require_extension('C');
   2 if (xlen == 32) {
   3   switch ((insn.bits() >> 5) & 3) {
   4     case 0: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S + insn.rvc_simm3())); // c.addin
   5     case 1: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S ^ insn.rvc_simm3())); // c.xorin
   6     case 2: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S | insn.rvc_simm3())); // c.orin
   7     case 3: WRITE_RVC_RS2S(sext_xlen(RVC_RS1S & insn.rvc_simm3())); // c.andin
   8   }
   9 } else {
  10   require(insn.rvc_rd() != 0);
  11   require(insn.rvc_imm() < 32);
  12   WRITE_RD(sext32(RVC_RS1 << insn.rvc_imm()));
  13 }