Implement clearing-misa.C-while-PC-is-misaligned proposal
[riscv-isa-sim.git] / riscv / insns / csrrsi.h
1 bool write = insn.rs1() != 0;
2 int csr = validate_csr(insn.csr(), write);
3 reg_t old = p->get_csr(csr);
4 if (write) {
5 p->set_csr(csr, old | insn.rs1());
6 }
7 WRITE_RD(sext_xlen(old));
8 serialize();