Merge pull request #156 from p12nGH/noncontiguous_harts

[riscv-isa-sim.git] / riscv / insns / fcvt_q_l.h

require_extension('Q');
require_rv64;
require_fp;
softfloat_roundingMode = RM;
WRITE_FRD(i64_to_f128(RS1));
set_fp_exceptions;