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Merge pull request #156 from p12nGH/noncontiguous_harts
[riscv-isa-sim.git] / riscv / insns / fcvt_q_s.h
1 require_extension('Q');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f32_to_f128(f32(FRS1)));
5 set_fp_exceptions;
Simple-V augmented version of spike