Merge pull request #156 from p12nGH/noncontiguous_harts
[riscv-isa-sim.git] / riscv / insns / fmax_d.h
1 require_extension('D');
2 require_fp;
3 bool greater = f64_lt_quiet(f64(FRS2), f64(FRS1)) ||
4 (f64_eq(f64(FRS2), f64(FRS1)) && (f64(FRS2).v & F64_SIGN));
5 if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
6 WRITE_FRD(f64(defaultNaNF64UI));
7 else
8 WRITE_FRD(greater || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
9 set_fp_exceptions;