Merge pull request #156 from p12nGH/noncontiguous_harts
[riscv-isa-sim.git] / riscv / insns / fmax_q.h
1 require_extension('Q');
2 require_fp;
3 bool greater = f128_lt_quiet(f128(FRS2), f128(FRS1)) ||
4 (f128_eq(f128(FRS2), f128(FRS1)) && (f128(FRS2).v[1] & F64_SIGN));
5 if (isNaNF128(f128(FRS1)) && isNaNF128(f128(FRS2)))
6 WRITE_FRD(f128(defaultNaNF128()));
7 else
8 WRITE_FRD(greater || isNaNF128(f128(FRS2)) ? FRS1 : FRS2);
9 set_fp_exceptions;