[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / fmin_d.h

require_fp;
FRD = isNaNF64UI(FRS2) || f64_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
      ? FRS1 : FRS2;
set_fp_exceptions;