Merge pull request #156 from p12nGH/noncontiguous_harts
[riscv-isa-sim.git] / riscv / insns / fnmsub_q.h
1 require_extension('Q');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f128_mulAdd(f128_negate(f128(FRS1)), f128(FRS2), f128(FRS3)));
5 set_fp_exceptions;