riscv/insns/mtc0.h

   1 require_supervisor;
   2
   3 switch(insn.rtype.rs)
   4 {
   5   case 0:
   6     set_sr(sext32(RT));
   7     break;
   8   case 1:
   9     epc = sext32(RT);
  10     break;
  11   case 3:
  12     ebase = sext32(RT & ~0xFFF);
  13     break;
  14   case 8:
  15     char ch = RT;
  16     demand(1 == write(1,&ch,1),"wtf");
  17     break;
  18 }