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HEAD
[xcc] minor performance tweaks
[riscv-isa-sim.git]
/
riscv
/
insns
/
mulhu.h
1
if
(
xpr64
)
2
RD
= (
uint128_t
(
RS1
) *
uint128_t
(
RS2
)) >>
64
;
3
else
4
RD
=
sext32
(((
uint64_t
)(
uint32_t
)
RS1
* (
uint64_t
)(
uint32_t
)
RS2
) >>
32
);