projects
/
riscv-isa-sim.git
/ blob
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
history
|
raw
|
HEAD
Refactor and fix LR/SC implementation (#217)
[riscv-isa-sim.git]
/
riscv
/
insns
/
sc_d.h
1
require_extension
(
'A'
);
2
require_rv64
;
3
if
(
MMU
.
check_load_reservation
(
RS1
))
4
{
5
MMU
.
store_uint64
(
RS1
,
RS2
);
6
WRITE_RD
(
0
);
7
}
8
else
9
WRITE_RD
(
1
);
10
11
MMU
.
yield_load_reservation
();