Refactor and fix LR/SC implementation (#217)
[riscv-isa-sim.git] / riscv / insns / sc_w.h
1 require_extension('A');
2 if (MMU.check_load_reservation(RS1))
3 {
4 MMU.store_uint32(RS1, RS2);
5 WRITE_RD(0);
6 }
7 else
8 WRITE_RD(1);
9
10 MMU.yield_load_reservation();