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Implement mstatus.TW, mstatus.TVM, and mstatus.TSR
[riscv-isa-sim.git] / riscv / insns / sfence_vma.h
1 require_privilege(get_field(STATE.mstatus, MSTATUS_TVM) ? PRV_M : PRV_S);
2 MMU.flush_tlb();
Simple-V augmented version of spike