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[xcc] minor performance tweaks
[riscv-isa-sim.git] / riscv / insns / vfmvv.h
1 require_vector;
2 require_fp;
3 UT_LOOP_START
4 UT_LOOP_FRD = UT_LOOP_FRS1;
5 UT_LOOP_END
Simple-V augmented version of spike