riscv/interactive.cc

   1 // See LICENSE for license details.
   2
   3 #include "decode.h"
   4 #include "disasm.h"
   5 #include "sim.h"
   6 #include "htif.h"
   7 #include <sys/mman.h>
   8 #include <termios.h>
   9 #include <map>
  10 #include <iostream>
  11 #include <climits>
  12 #include <cinttypes>
  13 #include <assert.h>
  14 #include <stdlib.h>
  15 #include <unistd.h>
  16 #include <sstream>
  17 #include <string>
  18 #include <vector>
  19 #include <algorithm>
  20
  21 processor_t *sim_t::get_core(const std::string& i)
  22 {
  23   char *ptr;
  24   unsigned long p = strtoul(i.c_str(), &ptr, 10);
  25   if (*ptr || p >= num_cores())
  26     throw trap_illegal_instruction();
  27   return get_core(p);
  28 }
  29
  30 static std::string readline(int fd)
  31 {
  32   struct termios tios;
  33   bool noncanonical = tcgetattr(fd, &tios) == 0 && (tios.c_lflag & ICANON) == 0;
  34
  35   std::string s;
  36   for (char ch; read(fd, &ch, 1) == 1; )
  37   {
  38     if (ch == '\x7f')
  39     {
  40       if (s.empty())
  41         continue;
  42       s.erase(s.end()-1);
  43
  44       if (noncanonical && write(fd, "\b \b", 3) != 3)
  45         ; // shut up gcc
  46     }
  47     else if (noncanonical && write(fd, &ch, 1) != 1)
  48       ; // shut up gcc
  49
  50     if (ch == '\n')
  51       break;
  52     if (ch != '\x7f')
  53       s += ch;
  54   }
  55   return s;
  56 }
  57
  58 void sim_t::interactive()
  59 {
  60   typedef void (sim_t::*interactive_func)(const std::string&, const std::vector<std::string>&);
  61   std::map<std::string,interactive_func> funcs;
  62
  63   funcs["run"] = &sim_t::interactive_run_noisy;
  64   funcs["r"] = funcs["run"];
  65   funcs["rs"] = &sim_t::interactive_run_silent;
  66   funcs["reg"] = &sim_t::interactive_reg;
  67   funcs["fregs"] = &sim_t::interactive_fregs;
  68   funcs["fregd"] = &sim_t::interactive_fregd;
  69   funcs["pc"] = &sim_t::interactive_pc;
  70   funcs["mem"] = &sim_t::interactive_mem;
  71   funcs["str"] = &sim_t::interactive_str;
  72   funcs["until"] = &sim_t::interactive_until;
  73   funcs["while"] = &sim_t::interactive_until;
  74   funcs["quit"] = &sim_t::interactive_quit;
  75   funcs["q"] = funcs["quit"];
  76   funcs["help"] = &sim_t::interactive_help;
  77   funcs["h"] = funcs["help"];
  78
  79   while (!htif->done())
  80   {
  81     std::cerr << ": " << std::flush;
  82     std::string s = readline(2);
  83
  84     std::stringstream ss(s);
  85     std::string cmd, tmp;
  86     std::vector<std::string> args;
  87
  88     if (!(ss >> cmd))
  89     {
  90       set_procs_debug(true);
  91       step(1);
  92       continue;
  93     }
  94
  95     while (ss >> tmp)
  96       args.push_back(tmp);
  97
  98     try
  99     {
 100       if(funcs.count(cmd))
 101         (this->*funcs[cmd])(cmd, args);
 102     }
 103     catch(trap_t t) {}
 104   }
 105   ctrlc_pressed = false;
 106 }
 107
 108 void sim_t::interactive_help(const std::string& cmd, const std::vector<std::string>& args)
 109 {
 110   std::cerr <<
 111     "Interactive commands:\n"
 112     "reg <core> <reg>                # Display <reg> in <core>\n"
 113     "fregs <core> <reg>              # Display single precision <reg> in <core>\n"
 114     "fregd <core> <reg>              # Display double precision <reg> in <core>\n"
 115     "pc <core>                       # Show current PC in <core>\n"
 116     "mem <hex addr>                  # Show contents of physical memory\n"
 117     "str <hex addr>                  # Show NUL-terminated C string\n"
 118     "until reg <core> <reg> <val>    # Stop when <reg> in <core> hits <val>\n"
 119     "until pc <core> <val>           # Stop when PC in <core> hits <val>\n"
 120     "until mem <addr> <val>          # Stop when memory <addr> becomes <val>\n"
 121     "while reg <core> <reg> <val>    # Run while <reg> in <core> is <val>\n"
 122     "while pc <core> <val>           # Run while PC in <core> is <val>\n"
 123     "while mem <addr> <val>          # Run while memory <addr> is <val>\n"
 124     "run [count]                     # Resume noisy execution (until CTRL+C, or [count] insns)\n"
 125     "r [count]                         Alias for run\n"
 126     "rs [count]                      # Resume silent execution (until CTRL+C, or [count] insns)\n"
 127     "quit                            # End the simulation\n"
 128     "q                                 Alias for quit\n"
 129     "help                            # This screen!\n"
 130     "h                                 Alias for help\n"
 131     "Note: Hitting enter is the same as: run 1\n"
 132     << std::flush;
 133 }
 134
 135 void sim_t::interactive_run_noisy(const std::string& cmd, const std::vector<std::string>& args)
 136 {
 137   interactive_run(cmd,args,true);
 138 }
 139
 140 void sim_t::interactive_run_silent(const std::string& cmd, const std::vector<std::string>& args)
 141 {
 142   interactive_run(cmd,args,false);
 143 }
 144
 145 void sim_t::interactive_run(const std::string& cmd, const std::vector<std::string>& args, bool noisy)
 146 {
 147   size_t steps = args.size() ? atoll(args[0].c_str()) : -1;
 148   ctrlc_pressed = false;
 149   set_procs_debug(noisy);
 150   for (size_t i = 0; i < steps && !ctrlc_pressed && !htif->done(); i++)
 151     step(1);
 152 }
 153
 154 void sim_t::interactive_quit(const std::string& cmd, const std::vector<std::string>& args)
 155 {
 156   exit(0);
 157 }
 158
 159 reg_t sim_t::get_pc(const std::vector<std::string>& args)
 160 {
 161   if(args.size() != 1)
 162     throw trap_illegal_instruction();
 163
 164   processor_t *p = get_core(args[0]);
 165   return p->state.pc;
 166 }
 167
 168 void sim_t::interactive_pc(const std::string& cmd, const std::vector<std::string>& args)
 169 {
 170   fprintf(stderr, "0x%016" PRIx64 "\n", get_pc(args));
 171 }
 172
 173 reg_t sim_t::get_reg(const std::vector<std::string>& args)
 174 {
 175   if(args.size() != 2)
 176     throw trap_illegal_instruction();
 177
 178   processor_t *p = get_core(args[0]);
 179
 180   unsigned long r = std::find(xpr_name, xpr_name + NXPR, args[1]) - xpr_name;
 181   if (r == NXPR) {
 182     char *ptr;
 183     r = strtoul(args[1].c_str(), &ptr, 10);
 184     if (*ptr) {
 185       #define DECLARE_CSR(name, number) if (args[1] == #name) return p->get_csr(number);
 186       if (0) ;
 187       #include "encoding.h"
 188       else r = NXPR;
 189       #undef DECLARE_CSR
 190     }
 191   }
 192
 193   if (r >= NXPR)
 194     throw trap_illegal_instruction();
 195
 196   return p->state.XPR[r];
 197 }
 198
 199 reg_t sim_t::get_freg(const std::vector<std::string>& args)
 200 {
 201   if(args.size() != 2)
 202     throw trap_illegal_instruction();
 203
 204   processor_t *p = get_core(args[0]);
 205   int r = std::find(fpr_name, fpr_name + NFPR, args[1]) - fpr_name;
 206   if (r == NFPR)
 207     r = atoi(args[1].c_str());
 208   if (r >= NFPR)
 209     throw trap_illegal_instruction();
 210
 211   return p->state.FPR[r];
 212 }
 213
 214 void sim_t::interactive_reg(const std::string& cmd, const std::vector<std::string>& args)
 215 {
 216   fprintf(stderr, "0x%016" PRIx64 "\n", get_reg(args));
 217 }
 218
 219 union fpr
 220 {
 221   reg_t r;
 222   float s;
 223   double d;
 224 };
 225
 226 void sim_t::interactive_fregs(const std::string& cmd, const std::vector<std::string>& args)
 227 {
 228   fpr f;
 229   f.r = get_freg(args);
 230   fprintf(stderr, "%g\n",f.s);
 231 }
 232
 233 void sim_t::interactive_fregd(const std::string& cmd, const std::vector<std::string>& args)
 234 {
 235   fpr f;
 236   f.r = get_freg(args);
 237   fprintf(stderr, "%g\n",f.d);
 238 }
 239
 240 reg_t sim_t::get_mem(const std::vector<std::string>& args)
 241 {
 242   if(args.size() != 1 && args.size() != 2)
 243     throw trap_illegal_instruction();
 244
 245   std::string addr_str = args[0];
 246   mmu_t* mmu = debug_mmu;
 247   if(args.size() == 2)
 248   {
 249     processor_t *p = get_core(args[0]);
 250     mmu = p->get_mmu();
 251     addr_str = args[1];
 252   }
 253
 254   reg_t addr = strtol(addr_str.c_str(),NULL,16), val;
 255   if(addr == LONG_MAX)
 256     addr = strtoul(addr_str.c_str(),NULL,16);
 257
 258   switch(addr % 8)
 259   {
 260     case 0:
 261       val = mmu->load_uint64(addr);
 262       break;
 263     case 4:
 264       val = mmu->load_uint32(addr);
 265       break;
 266     case 2:
 267     case 6:
 268       val = mmu->load_uint16(addr);
 269       break;
 270     default:
 271       val = mmu->load_uint8(addr);
 272       break;
 273   }
 274   return val;
 275 }
 276
 277 void sim_t::interactive_mem(const std::string& cmd, const std::vector<std::string>& args)
 278 {
 279   fprintf(stderr, "0x%016" PRIx64 "\n", get_mem(args));
 280 }
 281
 282 void sim_t::interactive_str(const std::string& cmd, const std::vector<std::string>& args)
 283 {
 284   if(args.size() != 1)
 285     throw trap_illegal_instruction();
 286
 287   reg_t addr = strtol(args[0].c_str(),NULL,16);
 288
 289   char ch;
 290   while((ch = debug_mmu->load_uint8(addr++)))
 291     putchar(ch);
 292
 293   putchar('\n');
 294 }
 295
 296 void sim_t::interactive_until(const std::string& cmd, const std::vector<std::string>& args)
 297 {
 298   bool cmd_until = cmd == "until";
 299
 300   if(args.size() < 3)
 301     return;
 302
 303   reg_t val = strtol(args[args.size()-1].c_str(),NULL,16);
 304   if(val == LONG_MAX)
 305     val = strtoul(args[args.size()-1].c_str(),NULL,16);
 306
 307   std::vector<std::string> args2;
 308   args2 = std::vector<std::string>(args.begin()+1,args.end()-1);
 309
 310   auto func = args[0] == "reg" ? &sim_t::get_reg :
 311               args[0] == "pc"  ? &sim_t::get_pc :
 312               args[0] == "mem" ? &sim_t::get_mem :
 313               NULL;
 314
 315   if (func == NULL)
 316     return;
 317
 318   ctrlc_pressed = false;
 319
 320   while (1)
 321   {
 322     try
 323     {
 324       reg_t current = (this->*func)(args2);
 325
 326       if (cmd_until == (current == val))
 327         break;
 328       if (ctrlc_pressed)
 329         break;
 330     }
 331     catch (trap_t t) {}
 332
 333     set_procs_debug(false);
 334     step(1);
 335   }
 336 }