riscv/mmu.cc

   1 #include "mmu.h"
   2 #include "sim.h"
   3 #include "processor.h"
   4
   5 mmu_t::mmu_t(char* _mem, size_t _memsz)
   6  : mem(_mem), memsz(_memsz), badvaddr(0),
   7    ptbr(0), supervisor(true), vm_enabled(false)
   8 {
   9   flush_tlb();
  10 }
  11
  12 mmu_t::~mmu_t()
  13 {
  14 }
  15
  16 void mmu_t::flush_tlb()
  17 {
  18   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  19   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  20   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  21
  22   flush_icache();
  23 }
  24
  25 void mmu_t::flush_icache()
  26 {
  27   memset(icache_tag, -1, sizeof(icache_tag));
  28 }
  29
  30 void* mmu_t::refill(reg_t addr, bool store, bool fetch)
  31 {
  32   reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
  33   reg_t expected_tag = addr & ~(PGSIZE-1);
  34
  35   reg_t pte = walk(addr);
  36
  37   reg_t pte_perm = pte & PTE_PERM;
  38   if(supervisor) // shift supervisor permission bits into user perm bits
  39     pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM;
  40   pte_perm |= pte & PTE_E;
  41
  42   reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_E;
  43   if(unlikely((pte_perm & perm) != perm))
  44   {
  45     badvaddr = addr;
  46     throw store ? trap_store_access_fault
  47         : fetch ? trap_instruction_access_fault
  48         :         trap_load_access_fault;
  49   }
  50
  51   tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
  52   tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
  53   tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
  54   tlb_data[idx] = (long)(pte >> PTE_PPN_SHIFT << PGSHIFT) + (long)mem;
  55
  56   return (void*)(((long)addr & (PGSIZE-1)) | tlb_data[idx]);
  57 }
  58
  59 pte_t mmu_t::walk(reg_t addr)
  60 {
  61   pte_t pte = 0;
  62
  63   if(!vm_enabled)
  64   {
  65     if(addr < memsz)
  66       pte = PTE_E | PTE_PERM | ((addr >> PGSHIFT) << PTE_PPN_SHIFT);
  67   }
  68   else
  69   {
  70     reg_t base = ptbr;
  71     reg_t ptd;
  72
  73     int ptshift = (LEVELS-1)*PTIDXBITS;
  74     for(reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS)
  75     {
  76       reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
  77
  78       reg_t pte_addr = base + idx*sizeof(pte_t);
  79       if(pte_addr >= memsz)
  80         break;
  81
  82       ptd = *(pte_t*)(mem+pte_addr);
  83       if(ptd & PTE_E)
  84       {
  85         // if this PTE is from a larger PT, fake a leaf
  86         // PTE so the TLB will work right
  87         reg_t vpn = addr >> PGSHIFT;
  88         ptd |= (vpn & ((1<<(ptshift))-1)) << PTE_PPN_SHIFT;
  89
  90         // fault if physical addr is invalid
  91         reg_t ppn = ptd >> PTE_PPN_SHIFT;
  92         if((ppn << PGSHIFT) + (addr & (PGSIZE-1)) < memsz)
  93           pte = ptd;
  94         break;
  95       }
  96       else if(!(ptd & PTE_T))
  97         break;
  98
  99       base = (ptd >> PTE_PPN_SHIFT) << PGSHIFT;
 100     }
 101   }
 102
 103   return pte;
 104 }