riscv/mmu.cc

   1 #include "mmu.h"
   2 #include "sim.h"
   3 #include "processor.h"
   4
   5 mmu_t::mmu_t(char* _mem, size_t _memsz)
   6  : mem(_mem), memsz(_memsz), badvaddr(0),
   7    ptbr(0), supervisor(true), vm_enabled(false)
   8 {
   9   flush_tlb();
  10 }
  11
  12 mmu_t::~mmu_t()
  13 {
  14 }
  15
  16 void mmu_t::flush_tlb()
  17 {
  18   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  19   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  20   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  21
  22   flush_icache();
  23 }
  24
  25 void mmu_t::flush_icache()
  26 {
  27   memset(icache_tag, -1, sizeof(icache_tag));
  28 }
  29
  30 void* mmu_t::refill(reg_t addr, bool store, bool fetch)
  31 {
  32   reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
  33   reg_t expected_tag = addr & ~(PGSIZE-1);
  34
  35   reg_t pte = walk(addr);
  36
  37   reg_t pte_perm = pte & PTE_PERM;
  38   if(supervisor) // shift supervisor permission bits into user perm bits
  39     pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM;
  40   pte_perm |= pte & PTE_E;
  41
  42   reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_E;
  43   if(unlikely((pte_perm & perm) != perm))
  44   {
  45     if (fetch)
  46       throw trap_instruction_access_fault;
  47
  48     badvaddr = addr;
  49     throw store ? trap_store_access_fault : trap_load_access_fault;
  50   }
  51
  52   tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
  53   tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
  54   tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
  55   tlb_data[idx] = (long)(pte >> PTE_PPN_SHIFT << PGSHIFT) + (long)mem;
  56
  57   return (void*)(((long)addr & (PGSIZE-1)) + tlb_data[idx]);
  58 }
  59
  60 pte_t mmu_t::walk(reg_t addr)
  61 {
  62   pte_t pte = 0;
  63
  64   // the address must be a canonical sign-extended VA_BITS-bit number
  65   int shift = 8*sizeof(reg_t) - VA_BITS;
  66   if (((sreg_t)addr << shift >> shift) != (sreg_t)addr)
  67     ;
  68   else if(!vm_enabled)
  69   {
  70     if(addr < memsz)
  71       pte = PTE_E | PTE_PERM | ((addr >> PGSHIFT) << PTE_PPN_SHIFT);
  72   }
  73   else
  74   {
  75     reg_t base = ptbr;
  76     reg_t ptd;
  77
  78     int ptshift = (LEVELS-1)*PTIDXBITS;
  79     for(reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS)
  80     {
  81       reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
  82
  83       reg_t pte_addr = base + idx*sizeof(pte_t);
  84       if(pte_addr >= memsz)
  85         break;
  86
  87       ptd = *(pte_t*)(mem+pte_addr);
  88       if(ptd & PTE_E)
  89       {
  90         // if this PTE is from a larger PT, fake a leaf
  91         // PTE so the TLB will work right
  92         reg_t vpn = addr >> PGSHIFT;
  93         ptd |= (vpn & ((1<<(ptshift))-1)) << PTE_PPN_SHIFT;
  94
  95         // fault if physical addr is invalid
  96         reg_t ppn = ptd >> PTE_PPN_SHIFT;
  97         if((ppn << PGSHIFT) + (addr & (PGSIZE-1)) < memsz)
  98           pte = ptd;
  99         break;
 100       }
 101       else if(!(ptd & PTE_T))
 102         break;
 103
 104       base = (ptd >> PTE_PPN_SHIFT) << PGSHIFT;
 105     }
 106   }
 107
 108   return pte;
 109 }