riscv/mmu.cc

   1 #include "mmu.h"
   2 #include "sim.h"
   3 #include "processor.h"
   4
   5 mmu_t::mmu_t(char* _mem, size_t _memsz)
   6  : mem(_mem), memsz(_memsz), badvaddr(0),
   7    ptbr(0), supervisor(true), vm_enabled(false)
   8 {
   9   flush_tlb();
  10 }
  11
  12 mmu_t::~mmu_t()
  13 {
  14 }
  15
  16 void mmu_t::flush_icache()
  17 {
  18   memset(icache_tag, -1, sizeof(icache_tag));
  19 }
  20
  21 void mmu_t::flush_tlb()
  22 {
  23   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  24   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  25   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  26
  27   flush_icache();
  28 }
  29
  30 reg_t mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
  31 {
  32   reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
  33   reg_t expected_tag = addr & ~(PGSIZE-1);
  34
  35   reg_t pte = walk(addr);
  36
  37   reg_t pte_perm = pte & PTE_PERM;
  38   if(supervisor) // shift supervisor permission bits into user perm bits
  39     pte_perm = (pte_perm/(PTE_SX/PTE_UX)) & PTE_PERM;
  40   pte_perm |= pte & PTE_E;
  41
  42   reg_t perm = (fetch ? PTE_UX : store ? PTE_UW : PTE_UR) | PTE_E;
  43   if(unlikely((pte_perm & perm) != perm))
  44   {
  45     if (fetch)
  46       throw trap_instruction_access_fault;
  47
  48     badvaddr = addr;
  49     throw store ? trap_store_access_fault : trap_load_access_fault;
  50   }
  51
  52   reg_t pgoff = addr & (PGSIZE-1);
  53   reg_t pgbase = pte >> PTE_PPN_SHIFT << PGSHIFT;
  54   reg_t paddr = pgbase + pgoff;
  55
  56   if (unlikely(tracer.interested_in_range(pgbase, pgbase + PGSIZE, store, fetch)))
  57     tracer.trace(paddr, bytes, store, fetch);
  58   else
  59   {
  60     tlb_load_tag[idx] = (pte_perm & PTE_UR) ? expected_tag : -1;
  61     tlb_store_tag[idx] = (pte_perm & PTE_UW) ? expected_tag : -1;
  62     tlb_insn_tag[idx] = (pte_perm & PTE_UX) ? expected_tag : -1;
  63     tlb_data[idx] = pgbase;
  64   }
  65
  66   return paddr;
  67 }
  68
  69 pte_t mmu_t::walk(reg_t addr)
  70 {
  71   pte_t pte = 0;
  72
  73   // the address must be a canonical sign-extended VA_BITS-bit number
  74   int shift = 8*sizeof(reg_t) - VA_BITS;
  75   if (((sreg_t)addr << shift >> shift) != (sreg_t)addr)
  76     ;
  77   else if(!vm_enabled)
  78   {
  79     if(addr < memsz)
  80       pte = PTE_E | PTE_PERM | ((addr >> PGSHIFT) << PTE_PPN_SHIFT);
  81   }
  82   else
  83   {
  84     reg_t base = ptbr;
  85     reg_t ptd;
  86
  87     int ptshift = (LEVELS-1)*PTIDXBITS;
  88     for(reg_t i = 0; i < LEVELS; i++, ptshift -= PTIDXBITS)
  89     {
  90       reg_t idx = (addr >> (PGSHIFT+ptshift)) & ((1<<PTIDXBITS)-1);
  91
  92       reg_t pte_addr = base + idx*sizeof(pte_t);
  93       if(pte_addr >= memsz)
  94         break;
  95
  96       ptd = *(pte_t*)(mem+pte_addr);
  97       if(ptd & PTE_E)
  98       {
  99         // if this PTE is from a larger PT, fake a leaf
 100         // PTE so the TLB will work right
 101         reg_t vpn = addr >> PGSHIFT;
 102         ptd |= (vpn & ((1<<(ptshift))-1)) << PTE_PPN_SHIFT;
 103
 104         // fault if physical addr is invalid
 105         reg_t ppn = ptd >> PTE_PPN_SHIFT;
 106         if((ppn << PGSHIFT) + (addr & (PGSIZE-1)) < memsz)
 107           pte = ptd;
 108         break;
 109       }
 110       else if(!(ptd & PTE_T))
 111         break;
 112
 113       base = (ptd >> PTE_PPN_SHIFT) << PGSHIFT;
 114     }
 115   }
 116
 117   return pte;
 118 }
 119
 120 void mmu_t::register_memtracer(memtracer_t* t)
 121 {
 122   flush_tlb();
 123   tracer.hook(t);
 124 }