riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(sim_t* sim, processor_t* proc)
   8  : sim(sim), proc(proc)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::translate(reg_t addr, access_type type)
  33 {
  34   if (!proc)
  35     return addr;
  36
  37   reg_t mode = proc->state.prv;
  38   bool pum = false;
  39   if (type != FETCH) {
  40     if (get_field(proc->state.mstatus, MSTATUS_MPRV))
  41       mode = get_field(proc->state.mstatus, MSTATUS_MPP);
  42     pum = (mode == PRV_S && get_field(proc->state.mstatus, MSTATUS_PUM));
  43   }
  44   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  45     mode = PRV_M;
  46
  47   if (mode == PRV_M) {
  48     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  49     return addr & msb_mask;
  50   }
  51   return walk(addr, type, mode > PRV_U, pum) | (addr & (PGSIZE-1));
  52 }
  53
  54 const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
  55 {
  56   reg_t paddr = translate(addr, FETCH);
  57
  58   if (sim->addr_is_mem(paddr)) {
  59     refill_tlb(addr, paddr, FETCH);
  60     return (const uint16_t*)sim->addr_to_mem(paddr);
  61   } else {
  62     if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp))
  63       throw trap_instruction_access_fault(addr);
  64     return &fetch_temp;
  65   }
  66 }
  67
  68 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
  69 {
  70   reg_t paddr = translate(addr, LOAD);
  71   if (sim->addr_is_mem(paddr)) {
  72     memcpy(bytes, sim->addr_to_mem(paddr), len);
  73     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
  74       tracer.trace(paddr, len, LOAD);
  75     else
  76       refill_tlb(addr, paddr, LOAD);
  77   } else if (!sim->mmio_load(paddr, len, bytes)) {
  78     throw trap_load_access_fault(addr);
  79   }
  80 }
  81
  82 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
  83 {
  84   reg_t paddr = translate(addr, STORE);
  85   if (sim->addr_is_mem(paddr)) {
  86     memcpy(sim->addr_to_mem(paddr), bytes, len);
  87     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
  88       tracer.trace(paddr, len, STORE);
  89     else
  90       refill_tlb(addr, paddr, STORE);
  91   } else if (!sim->mmio_store(paddr, len, bytes)) {
  92     throw trap_store_access_fault(addr);
  93   }
  94 }
  95
  96 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
  97 {
  98   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
  99   reg_t expected_tag = vaddr >> PGSHIFT;
 100
 101   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
 102   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
 103   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
 104
 105   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
 106   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
 107   else tlb_load_tag[idx] = expected_tag;
 108
 109   tlb_data[idx] = sim->addr_to_mem(paddr) - vaddr;
 110 }
 111
 112 reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
 113 {
 114   int levels, ptidxbits, ptesize;
 115   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 116   {
 117     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 118     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 119     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 120     default: abort();
 121   }
 122
 123   // verify bits xlen-1:va_bits-1 are all equal
 124   int va_bits = PGSHIFT + levels * ptidxbits;
 125   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 126   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 127   if (masked_msbs != 0 && masked_msbs != mask)
 128     return -1;
 129
 130   reg_t base = proc->get_state()->sptbr << PGSHIFT;
 131   int ptshift = (levels - 1) * ptidxbits;
 132   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 133     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 134
 135     // check that physical address of PTE is legal
 136     reg_t pte_addr = base + idx * ptesize;
 137     if (!sim->addr_is_mem(pte_addr))
 138       break;
 139
 140     void* ppte = sim->addr_to_mem(pte_addr);
 141     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 142     reg_t ppn = pte >> PTE_PPN_SHIFT;
 143
 144     if (PTE_TABLE(pte)) { // next level of page table
 145       base = ppn << PGSHIFT;
 146     } else if (pum && PTE_CHECK_PERM(pte, 0, type == STORE, type == FETCH)) {
 147       break;
 148     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
 149       break;
 150     } else {
 151       // set referenced and possibly dirty bits.
 152       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
 153       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 154       reg_t vpn = addr >> PGSHIFT;
 155       return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 156     }
 157   }
 158
 159   return -1;
 160 }
 161
 162 void mmu_t::register_memtracer(memtracer_t* t)
 163 {
 164   flush_tlb();
 165   tracer.hook(t);
 166 }