riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(sim_t* sim, processor_t* proc)
   8  : sim(sim), proc(proc)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::translate(reg_t addr, access_type type)
  33 {
  34   if (!proc)
  35     return addr;
  36
  37   reg_t mode = proc->state.prv;
  38   bool pum = false;
  39   if (type != FETCH) {
  40     if (get_field(proc->state.mstatus, MSTATUS_MPRV))
  41       mode = get_field(proc->state.mstatus, MSTATUS_MPP);
  42     pum = (mode == PRV_S && get_field(proc->state.mstatus, MSTATUS_PUM));
  43   }
  44   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  45     mode = PRV_M;
  46
  47   fprintf(stderr, "translate(0x%lx, %d), mstatus=0x%lx, prv=%ld, mode=%ld, pum=%d\n",
  48       addr, type, proc->state.mstatus, proc->state.prv, mode, pum);
  49   if (mode == PRV_M) {
  50     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  51     return addr & msb_mask;
  52   }
  53   return walk(addr, type, mode > PRV_U, pum) | (addr & (PGSIZE-1));
  54 }
  55
  56 const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr)
  57 {
  58   reg_t paddr = translate(vaddr, FETCH);
  59
  60   // mmu_t::walk() returns -1 if it can't find a match. Of course -1 could also
  61   // be a valid address.
  62   if (paddr == ~(reg_t) 0 && vaddr != ~(reg_t) 0) {
  63     throw trap_instruction_access_fault(vaddr);
  64   }
  65
  66   if (sim->addr_is_mem(paddr)) {
  67     refill_tlb(vaddr, paddr, FETCH);
  68     return (const uint16_t*)sim->addr_to_mem(paddr);
  69   } else {
  70     if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp))
  71       throw trap_instruction_access_fault(vaddr);
  72     return &fetch_temp;
  73   }
  74 }
  75
  76 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
  77 {
  78   reg_t paddr = translate(addr, LOAD);
  79   fprintf(stderr, "load_slow_path 0x%lx -> 0x%lx\n", addr, paddr);
  80   if (sim->addr_is_mem(paddr)) {
  81     memcpy(bytes, sim->addr_to_mem(paddr), len);
  82     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
  83       tracer.trace(paddr, len, LOAD);
  84     else
  85       refill_tlb(addr, paddr, LOAD);
  86   } else if (!sim->mmio_load(paddr, len, bytes)) {
  87     throw trap_load_access_fault(addr);
  88   }
  89 }
  90
  91 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
  92 {
  93   reg_t paddr = translate(addr, STORE);
  94   fprintf(stderr, "store_slow_path 0x%lx -> 0x%lx\n", addr, paddr);
  95   if (sim->addr_is_mem(paddr)) {
  96     memcpy(sim->addr_to_mem(paddr), bytes, len);
  97     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
  98       tracer.trace(paddr, len, STORE);
  99     else
 100       refill_tlb(addr, paddr, STORE);
 101   } else if (!sim->mmio_store(paddr, len, bytes)) {
 102     throw trap_store_access_fault(addr);
 103   }
 104 }
 105
 106 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
 107 {
 108   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
 109   reg_t expected_tag = vaddr >> PGSHIFT;
 110
 111   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
 112   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
 113   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
 114
 115   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
 116   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
 117   else tlb_load_tag[idx] = expected_tag;
 118
 119   tlb_data[idx] = sim->addr_to_mem(paddr) - vaddr;
 120 }
 121
 122 reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
 123 {
 124   int levels, ptidxbits, ptesize;
 125   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 126   {
 127     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 128     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 129     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 130     default: abort();
 131   }
 132
 133   // verify bits xlen-1:va_bits-1 are all equal
 134   int va_bits = PGSHIFT + levels * ptidxbits;
 135   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 136   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 137   if (masked_msbs != 0 && masked_msbs != mask)
 138     return -1;
 139
 140   reg_t base = proc->get_state()->sptbr << PGSHIFT;
 141   int ptshift = (levels - 1) * ptidxbits;
 142   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 143     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 144
 145     // check that physical address of PTE is legal
 146     reg_t pte_addr = base + idx * ptesize;
 147     if (!sim->addr_is_mem(pte_addr))
 148       break;
 149
 150     void* ppte = sim->addr_to_mem(pte_addr);
 151     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 152     reg_t ppn = pte >> PTE_PPN_SHIFT;
 153
 154     if (PTE_TABLE(pte)) { // next level of page table
 155       base = ppn << PGSHIFT;
 156     } else if (pum && PTE_CHECK_PERM(pte, 0, type == STORE, type == FETCH)) {
 157       break;
 158     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
 159       break;
 160     } else {
 161       // set referenced and possibly dirty bits.
 162       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
 163       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 164       reg_t vpn = addr >> PGSHIFT;
 165       return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 166     }
 167   }
 168
 169   return -1;
 170 }
 171
 172 void mmu_t::register_memtracer(memtracer_t* t)
 173 {
 174   flush_tlb();
 175   tracer.hook(t);
 176 }