riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(char* _mem, size_t _memsz)
   8  : mem(_mem), memsz(_memsz), proc(NULL)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::translate(reg_t addr, access_type type)
  33 {
  34   if (!proc)
  35     return addr;
  36
  37   reg_t mode = get_field(proc->state.mstatus, MSTATUS_PRV);
  38   if (type != FETCH && get_field(proc->state.mstatus, MSTATUS_MPRV))
  39     mode = get_field(proc->state.mstatus, MSTATUS_PRV1);
  40   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  41     mode = PRV_M;
  42
  43   if (mode == PRV_M) {
  44     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  45     return addr & msb_mask;
  46   }
  47   return walk(addr, mode > PRV_U, type) | (addr & (PGSIZE-1));
  48 }
  49
  50 const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
  51 {
  52   reg_t paddr = translate(addr, FETCH);
  53   if (paddr >= memsz)
  54     throw trap_instruction_access_fault(addr);
  55   return (const uint16_t*)(mem + paddr);
  56 }
  57
  58 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
  59 {
  60   reg_t paddr = translate(addr, LOAD);
  61   if (paddr < memsz) {
  62     memcpy(bytes, mem + paddr, len);
  63     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
  64       tracer.trace(paddr, len, LOAD);
  65     else
  66       refill_tlb(addr, paddr, LOAD);
  67   } else if (!proc || !proc->sim->mmio_load(addr, len, bytes)) {
  68     throw trap_load_access_fault(addr);
  69   }
  70 }
  71
  72 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
  73 {
  74   reg_t paddr = translate(addr, STORE);
  75   if (paddr < memsz) {
  76     memcpy(mem + paddr, bytes, len);
  77     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
  78       tracer.trace(paddr, len, STORE);
  79     else
  80       refill_tlb(addr, paddr, STORE);
  81   } else if (!proc || !proc->sim->mmio_store(addr, len, bytes)) {
  82     throw trap_store_access_fault(addr);
  83   }
  84 }
  85
  86 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
  87 {
  88   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
  89   reg_t expected_tag = vaddr >> PGSHIFT;
  90
  91   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
  92   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
  93   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
  94
  95   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
  96   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
  97   else tlb_load_tag[idx] = expected_tag;
  98
  99   tlb_data[idx] = mem + paddr - vaddr;
 100 }
 101
 102 reg_t mmu_t::walk(reg_t addr, bool supervisor, access_type type)
 103 {
 104   int levels, ptidxbits, ptesize;
 105   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 106   {
 107     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 108     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 109     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 110     default: abort();
 111   }
 112
 113   // verify bits xlen-1:va_bits-1 are all equal
 114   int va_bits = PGSHIFT + levels * ptidxbits;
 115   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 116   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 117   if (masked_msbs != 0 && masked_msbs != mask)
 118     return -1;
 119
 120   reg_t base = proc->get_state()->sptbr;
 121   int ptshift = (levels - 1) * ptidxbits;
 122   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 123     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 124
 125     // check that physical address of PTE is legal
 126     reg_t pte_addr = base + idx * ptesize;
 127     if (pte_addr >= memsz)
 128       break;
 129
 130     void* ppte = mem + pte_addr;
 131     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 132     reg_t ppn = pte >> PTE_PPN_SHIFT;
 133
 134     if (PTE_TABLE(pte)) { // next level of page table
 135       base = ppn << PGSHIFT;
 136     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
 137       break;
 138     } else {
 139       // set referenced and possibly dirty bits.
 140       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
 141       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 142       reg_t vpn = addr >> PGSHIFT;
 143       return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 144     }
 145   }
 146
 147   return -1;
 148 }
 149
 150 void mmu_t::register_memtracer(memtracer_t* t)
 151 {
 152   flush_tlb();
 153   tracer.hook(t);
 154 }