riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(char* _mem, size_t _memsz)
   8  : mem(_mem), memsz(_memsz), proc(NULL)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::translate(reg_t addr, access_type type)
  33 {
  34   if (!proc)
  35     return addr;
  36
  37   reg_t mode = get_field(proc->state.mstatus, MSTATUS_PRV);
  38   if (type != FETCH && get_field(proc->state.mstatus, MSTATUS_MPRV))
  39     mode = get_field(proc->state.mstatus, MSTATUS_PRV1);
  40   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  41     mode = PRV_M;
  42
  43   if (mode == PRV_M) {
  44     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  45     return addr & msb_mask;
  46   }
  47   return walk(addr, mode > PRV_U, type) | (addr & (PGSIZE-1));
  48 }
  49
  50 const uint16_t* mmu_t::fetch_slow_path(reg_t addr)
  51 {
  52   reg_t paddr = translate(addr, FETCH);
  53   if (paddr < memsz)
  54     refill_tlb(addr, paddr, FETCH);
  55   else
  56     throw trap_instruction_access_fault(addr);
  57   return (const uint16_t*)(mem + paddr);
  58 }
  59
  60 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
  61 {
  62   reg_t paddr = translate(addr, LOAD);
  63   if (paddr < memsz) {
  64     memcpy(bytes, mem + paddr, len);
  65     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
  66       tracer.trace(paddr, len, LOAD);
  67     else
  68       refill_tlb(addr, paddr, LOAD);
  69   } else if (!proc || !proc->sim->mmio_load(paddr, len, bytes)) {
  70     throw trap_load_access_fault(addr);
  71   }
  72 }
  73
  74 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
  75 {
  76   reg_t paddr = translate(addr, STORE);
  77   if (paddr < memsz) {
  78     memcpy(mem + paddr, bytes, len);
  79     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
  80       tracer.trace(paddr, len, STORE);
  81     else
  82       refill_tlb(addr, paddr, STORE);
  83   } else if (!proc || !proc->sim->mmio_store(paddr, len, bytes)) {
  84     throw trap_store_access_fault(addr);
  85   }
  86 }
  87
  88 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
  89 {
  90   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
  91   reg_t expected_tag = vaddr >> PGSHIFT;
  92
  93   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
  94   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
  95   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
  96
  97   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
  98   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
  99   else tlb_load_tag[idx] = expected_tag;
 100
 101   tlb_data[idx] = mem + paddr - vaddr;
 102 }
 103
 104 reg_t mmu_t::walk(reg_t addr, bool supervisor, access_type type)
 105 {
 106   int levels, ptidxbits, ptesize;
 107   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 108   {
 109     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 110     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 111     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 112     default: abort();
 113   }
 114
 115   // verify bits xlen-1:va_bits-1 are all equal
 116   int va_bits = PGSHIFT + levels * ptidxbits;
 117   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 118   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 119   if (masked_msbs != 0 && masked_msbs != mask)
 120     return -1;
 121
 122   reg_t base = proc->get_state()->sptbr;
 123   int ptshift = (levels - 1) * ptidxbits;
 124   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 125     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 126
 127     // check that physical address of PTE is legal
 128     reg_t pte_addr = base + idx * ptesize;
 129     if (pte_addr >= memsz)
 130       break;
 131
 132     void* ppte = mem + pte_addr;
 133     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 134     reg_t ppn = pte >> PTE_PPN_SHIFT;
 135
 136     if (PTE_TABLE(pte)) { // next level of page table
 137       base = ppn << PGSHIFT;
 138     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
 139       break;
 140     } else {
 141       // set referenced and possibly dirty bits.
 142       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
 143       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 144       reg_t vpn = addr >> PGSHIFT;
 145       return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 146     }
 147   }
 148
 149   return -1;
 150 }
 151
 152 void mmu_t::register_memtracer(memtracer_t* t)
 153 {
 154   flush_tlb();
 155   tracer.hook(t);
 156 }