riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(sim_t* sim, processor_t* proc)
   8  : sim(sim), proc(proc),
   9   check_triggers_fetch(false),
  10   check_triggers_load(false),
  11   check_triggers_store(false),
  12   matched_trigger(NULL)
  13 {
  14   flush_tlb();
  15 }
  16
  17 mmu_t::~mmu_t()
  18 {
  19 }
  20
  21 void mmu_t::flush_icache()
  22 {
  23   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  24     icache[i].tag = -1;
  25 }
  26
  27 void mmu_t::flush_tlb()
  28 {
  29   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  30   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  31   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  32
  33   flush_icache();
  34 }
  35
  36 reg_t mmu_t::translate(reg_t addr, access_type type)
  37 {
  38   if (!proc)
  39     return addr;
  40
  41   reg_t mode = proc->state.prv;
  42   if (type != FETCH) {
  43     if (!proc->state.dcsr.cause && get_field(proc->state.mstatus, MSTATUS_MPRV))
  44       mode = get_field(proc->state.mstatus, MSTATUS_MPP);
  45   }
  46   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  47     mode = PRV_M;
  48
  49   if (mode == PRV_M) {
  50     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  51     return addr & msb_mask;
  52   }
  53   return walk(addr, type, mode) | (addr & (PGSIZE-1));
  54 }
  55
  56 const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr)
  57 {
  58   reg_t paddr = translate(vaddr, FETCH);
  59
  60   // mmu_t::walk() returns -1 if it can't find a match. Of course -1 could also
  61   // be a valid address.
  62   if (paddr == ~(reg_t) 0 && vaddr != ~(reg_t) 0) {
  63     throw trap_instruction_access_fault(vaddr);
  64   }
  65
  66   if (sim->addr_is_mem(paddr)) {
  67     refill_tlb(vaddr, paddr, FETCH);
  68     return (const uint16_t*)sim->addr_to_mem(paddr);
  69   } else {
  70     if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp))
  71       throw trap_instruction_access_fault(vaddr);
  72     return &fetch_temp;
  73   }
  74 }
  75
  76 reg_t reg_from_bytes(size_t len, const uint8_t* bytes)
  77 {
  78   switch (len) {
  79     case 1:
  80       return bytes[0];
  81     case 2:
  82       return bytes[0] |
  83         (((reg_t) bytes[1]) << 8);
  84     case 4:
  85       return bytes[0] |
  86         (((reg_t) bytes[1]) << 8) |
  87         (((reg_t) bytes[2]) << 16) |
  88         (((reg_t) bytes[3]) << 24);
  89     case 8:
  90       return bytes[0] |
  91         (((reg_t) bytes[1]) << 8) |
  92         (((reg_t) bytes[2]) << 16) |
  93         (((reg_t) bytes[3]) << 24) |
  94         (((reg_t) bytes[4]) << 32) |
  95         (((reg_t) bytes[5]) << 40) |
  96         (((reg_t) bytes[6]) << 48) |
  97         (((reg_t) bytes[7]) << 56);
  98   }
  99   abort();
 100 }
 101
 102 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
 103 {
 104   reg_t paddr = translate(addr, LOAD);
 105
 106   if (sim->addr_is_mem(paddr)) {
 107     memcpy(bytes, sim->addr_to_mem(paddr), len);
 108     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
 109       tracer.trace(paddr, len, LOAD);
 110     else
 111       refill_tlb(addr, paddr, LOAD);
 112   } else if (!sim->mmio_load(paddr, len, bytes)) {
 113     throw trap_load_access_fault(addr);
 114   }
 115
 116   if (!matched_trigger) {
 117     reg_t data = reg_from_bytes(len, bytes);
 118     matched_trigger = trigger_exception(OPERATION_LOAD, addr, data);
 119     if (matched_trigger)
 120       throw *matched_trigger;
 121   }
 122 }
 123
 124 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
 125 {
 126   reg_t paddr = translate(addr, STORE);
 127
 128   if (!matched_trigger) {
 129     reg_t data = reg_from_bytes(len, bytes);
 130     matched_trigger = trigger_exception(OPERATION_STORE, addr, data);
 131     if (matched_trigger)
 132       throw *matched_trigger;
 133   }
 134
 135   if (sim->addr_is_mem(paddr)) {
 136     memcpy(sim->addr_to_mem(paddr), bytes, len);
 137     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
 138       tracer.trace(paddr, len, STORE);
 139     else
 140       refill_tlb(addr, paddr, STORE);
 141   } else if (!sim->mmio_store(paddr, len, bytes)) {
 142     throw trap_store_access_fault(addr);
 143   }
 144 }
 145
 146 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
 147 {
 148   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
 149   reg_t expected_tag = vaddr >> PGSHIFT;
 150
 151   if ((tlb_load_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag)
 152     tlb_load_tag[idx] = -1;
 153   if ((tlb_store_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag)
 154     tlb_store_tag[idx] = -1;
 155   if ((tlb_insn_tag[idx] & ~TLB_CHECK_TRIGGERS) != expected_tag)
 156     tlb_insn_tag[idx] = -1;
 157
 158   if ((check_triggers_fetch && type == FETCH) ||
 159       (check_triggers_load && type == LOAD) ||
 160       (check_triggers_store && type == STORE))
 161     expected_tag |= TLB_CHECK_TRIGGERS;
 162
 163   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
 164   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
 165   else tlb_load_tag[idx] = expected_tag;
 166
 167   tlb_data[idx] = sim->addr_to_mem(paddr) - vaddr;
 168 }
 169
 170 reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
 171 {
 172   int levels, ptidxbits, ptesize;
 173   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 174   {
 175     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 176     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 177     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 178     default: abort();
 179   }
 180
 181   bool supervisor = mode == PRV_S;
 182   bool pum = get_field(proc->state.mstatus, MSTATUS_PUM);
 183   bool mxr = get_field(proc->state.mstatus, MSTATUS_MXR);
 184
 185   // verify bits xlen-1:va_bits-1 are all equal
 186   int va_bits = PGSHIFT + levels * ptidxbits;
 187   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 188   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 189   if (masked_msbs != 0 && masked_msbs != mask)
 190     return -1;
 191
 192   reg_t base = proc->get_state()->sptbr << PGSHIFT;
 193   int ptshift = (levels - 1) * ptidxbits;
 194   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 195     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 196
 197     // check that physical address of PTE is legal
 198     reg_t pte_addr = base + idx * ptesize;
 199     if (!sim->addr_is_mem(pte_addr))
 200       break;
 201
 202     void* ppte = sim->addr_to_mem(pte_addr);
 203     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 204     reg_t ppn = pte >> PTE_PPN_SHIFT;
 205
 206     if (PTE_TABLE(pte)) { // next level of page table
 207       base = ppn << PGSHIFT;
 208     } else if ((pte & PTE_U) ? supervisor && pum : !supervisor) {
 209       break;
 210     } else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
 211       break;
 212     } else if (type == FETCH ? !(pte & PTE_X) :
 213                type == LOAD ?  !(pte & PTE_R) && !(mxr && (pte & PTE_X)) :
 214                                !((pte & PTE_R) && (pte & PTE_W))) {
 215       break;
 216     } else {
 217       // set accessed and possibly dirty bits.
 218       *(uint32_t*)ppte |= PTE_A | ((type == STORE) * PTE_D);
 219       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 220       reg_t vpn = addr >> PGSHIFT;
 221       reg_t value = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 222       return value;
 223     }
 224   }
 225
 226   return -1;
 227 }
 228
 229 void mmu_t::register_memtracer(memtracer_t* t)
 230 {
 231   flush_tlb();
 232   tracer.hook(t);
 233 }