riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(sim_t* sim, processor_t* proc)
   8  : sim(sim), proc(proc)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 reg_t mmu_t::translate(reg_t addr, access_type type)
  33 {
  34   if (!proc)
  35     return addr;
  36
  37   reg_t mode = proc->state.prv;
  38   bool pum = false;
  39   if (type != FETCH) {
  40     if (get_field(proc->state.mstatus, MSTATUS_MPRV))
  41       mode = get_field(proc->state.mstatus, MSTATUS_MPP);
  42     pum = (mode == PRV_S && get_field(proc->state.mstatus, MSTATUS_PUM));
  43   }
  44   if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  45     mode = PRV_M;
  46
  47   if (mode == PRV_M) {
  48     reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  49     return addr & msb_mask;
  50   }
  51   return walk(addr, type, mode > PRV_U, pum) | (addr & (PGSIZE-1));
  52 }
  53
  54 const char* mmu_t::fill_from_mmio(reg_t vaddr, reg_t paddr)
  55 {
  56   reg_t rv_start = paddr & PGMASK;
  57   char* spike_start = proc->sim->mmio_page(rv_start);
  58
  59   if (!spike_start)
  60     return NULL;
  61
  62   // TODO: refactor with refill_tlb()
  63   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
  64   reg_t expected_tag = vaddr >> PGSHIFT;
  65
  66   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
  67   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
  68   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
  69
  70   tlb_insn_tag[idx] = expected_tag;
  71   tlb_data[idx] = spike_start - DEBUG_START;
  72
  73   return spike_start + (paddr & ~PGMASK);
  74 }
  75
  76 const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr)
  77 {
  78   reg_t paddr = translate(vaddr, FETCH);
  79
  80   // mmu_t::walk() returns -1 if it can't find a match. Of course -1 could also
  81   // be a valid address.
  82   if (paddr == ~(reg_t) 0 && vaddr != ~(reg_t) 0) {
  83     throw trap_instruction_access_fault(vaddr);
  84   }
  85
  86   if (sim->addr_is_mem(paddr)) {
  87     refill_tlb(vaddr, paddr, FETCH);
  88     return (const uint16_t*)sim->addr_to_mem(paddr);
  89   } else {
  90     if (!sim->mmio_load(paddr, sizeof fetch_temp, (uint8_t*)&fetch_temp))
  91       throw trap_instruction_access_fault(vaddr);
  92     return &fetch_temp;
  93   }
  94 }
  95
  96 void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes)
  97 {
  98   reg_t paddr = translate(addr, LOAD);
  99   if (sim->addr_is_mem(paddr)) {
 100     memcpy(bytes, sim->addr_to_mem(paddr), len);
 101     if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD))
 102       tracer.trace(paddr, len, LOAD);
 103     else
 104       refill_tlb(addr, paddr, LOAD);
 105   } else if (!sim->mmio_load(paddr, len, bytes)) {
 106     throw trap_load_access_fault(addr);
 107   }
 108 }
 109
 110 void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes)
 111 {
 112   reg_t paddr = translate(addr, STORE);
 113   if (sim->addr_is_mem(paddr)) {
 114     memcpy(sim->addr_to_mem(paddr), bytes, len);
 115     if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE))
 116       tracer.trace(paddr, len, STORE);
 117     else
 118       refill_tlb(addr, paddr, STORE);
 119   } else if (!sim->mmio_store(paddr, len, bytes)) {
 120     throw trap_store_access_fault(addr);
 121   }
 122 }
 123
 124 void mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, access_type type)
 125 {
 126   reg_t idx = (vaddr >> PGSHIFT) % TLB_ENTRIES;
 127   reg_t expected_tag = vaddr >> PGSHIFT;
 128
 129   if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
 130   if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
 131   if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
 132
 133   if (type == FETCH) tlb_insn_tag[idx] = expected_tag;
 134   else if (type == STORE) tlb_store_tag[idx] = expected_tag;
 135   else tlb_load_tag[idx] = expected_tag;
 136
 137   tlb_data[idx] = sim->addr_to_mem(paddr) - vaddr;
 138 }
 139
 140 reg_t mmu_t::walk(reg_t addr, access_type type, bool supervisor, bool pum)
 141 {
 142   int levels, ptidxbits, ptesize;
 143   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
 144   {
 145     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
 146     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
 147     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
 148     default: abort();
 149   }
 150
 151   // verify bits xlen-1:va_bits-1 are all equal
 152   int va_bits = PGSHIFT + levels * ptidxbits;
 153   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
 154   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
 155   if (masked_msbs != 0 && masked_msbs != mask)
 156     return -1;
 157
 158   reg_t base = proc->get_state()->sptbr << PGSHIFT;
 159   int ptshift = (levels - 1) * ptidxbits;
 160   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 161     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 162
 163     // check that physical address of PTE is legal
 164     reg_t pte_addr = base + idx * ptesize;
 165     if (!sim->addr_is_mem(pte_addr))
 166       break;
 167
 168     void* ppte = sim->addr_to_mem(pte_addr);
 169     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 170     reg_t ppn = pte >> PTE_PPN_SHIFT;
 171
 172     if (PTE_TABLE(pte)) { // next level of page table
 173       base = ppn << PGSHIFT;
 174     } else if (pum && PTE_CHECK_PERM(pte, 0, type == STORE, type == FETCH)) {
 175       break;
 176     } else if (!PTE_CHECK_PERM(pte, supervisor, type == STORE, type == FETCH)) {
 177       break;
 178     } else {
 179       // set referenced and possibly dirty bits.
 180       *(uint32_t*)ppte |= PTE_R | ((type == STORE) * PTE_D);
 181       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 182       reg_t vpn = addr >> PGSHIFT;
 183       return (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 184     }
 185   }
 186
 187   return -1;
 188 }
 189
 190 void mmu_t::register_memtracer(memtracer_t* t)
 191 {
 192   flush_tlb();
 193   tracer.hook(t);
 194 }