riscv/mmu.cc

   1 // See LICENSE for license details.
   2
   3 #include "mmu.h"
   4 #include "sim.h"
   5 #include "processor.h"
   6
   7 mmu_t::mmu_t(char* _mem, size_t _memsz)
   8  : mem(_mem), memsz(_memsz), proc(NULL)
   9 {
  10   flush_tlb();
  11 }
  12
  13 mmu_t::~mmu_t()
  14 {
  15 }
  16
  17 void mmu_t::flush_icache()
  18 {
  19   for (size_t i = 0; i < ICACHE_ENTRIES; i++)
  20     icache[i].tag = -1;
  21 }
  22
  23 void mmu_t::flush_tlb()
  24 {
  25   memset(tlb_insn_tag, -1, sizeof(tlb_insn_tag));
  26   memset(tlb_load_tag, -1, sizeof(tlb_load_tag));
  27   memset(tlb_store_tag, -1, sizeof(tlb_store_tag));
  28
  29   flush_icache();
  30 }
  31
  32 void* mmu_t::refill_tlb(reg_t addr, reg_t bytes, bool store, bool fetch)
  33 {
  34   reg_t idx = (addr >> PGSHIFT) % TLB_ENTRIES;
  35   reg_t expected_tag = addr >> PGSHIFT;
  36
  37   reg_t pgbase;
  38   if (unlikely(!proc)) {
  39     pgbase = addr & -PGSIZE;
  40   } else {
  41     reg_t mode = get_field(proc->state.mstatus, MSTATUS_PRV);
  42     if (!fetch && get_field(proc->state.mstatus, MSTATUS_MPRV))
  43       mode = get_field(proc->state.mstatus, MSTATUS_PRV1);
  44     if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE)
  45       mode = PRV_M;
  46
  47     if (mode == PRV_M) {
  48       reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen
  49       pgbase = addr & -PGSIZE & msb_mask;
  50     } else {
  51       pgbase = walk(addr, mode > PRV_U, store, fetch);
  52     }
  53   }
  54
  55   reg_t pgoff = addr & (PGSIZE-1);
  56   reg_t paddr = pgbase + pgoff;
  57
  58   if (pgbase >= memsz) {
  59     if (fetch) throw trap_instruction_access_fault(addr);
  60     else if (store) throw trap_store_access_fault(addr);
  61     else throw trap_load_access_fault(addr);
  62   }
  63
  64   bool trace = tracer.interested_in_range(pgbase, pgbase + PGSIZE, store, fetch);
  65   if (unlikely(!fetch && trace))
  66     tracer.trace(paddr, bytes, store, fetch);
  67   else
  68   {
  69     if (tlb_load_tag[idx] != expected_tag) tlb_load_tag[idx] = -1;
  70     if (tlb_store_tag[idx] != expected_tag) tlb_store_tag[idx] = -1;
  71     if (tlb_insn_tag[idx] != expected_tag) tlb_insn_tag[idx] = -1;
  72
  73     if (fetch) tlb_insn_tag[idx] = expected_tag;
  74     else if (store) tlb_store_tag[idx] = expected_tag;
  75     else tlb_load_tag[idx] = expected_tag;
  76
  77     tlb_data[idx] = mem + pgbase - (addr & -PGSIZE);
  78   }
  79
  80   return mem + paddr;
  81 }
  82
  83 reg_t mmu_t::walk(reg_t addr, bool supervisor, bool store, bool fetch)
  84 {
  85   int levels, ptidxbits, ptesize;
  86   switch (get_field(proc->get_state()->mstatus, MSTATUS_VM))
  87   {
  88     case VM_SV32: levels = 2; ptidxbits = 10; ptesize = 4; break;
  89     case VM_SV39: levels = 3; ptidxbits = 9; ptesize = 8; break;
  90     case VM_SV48: levels = 4; ptidxbits = 9; ptesize = 8; break;
  91     default: abort();
  92   }
  93
  94   // verify bits xlen-1:va_bits-1 are all equal
  95   int va_bits = PGSHIFT + levels * ptidxbits;
  96   reg_t mask = (reg_t(1) << (proc->xlen - (va_bits-1))) - 1;
  97   reg_t masked_msbs = (addr >> (va_bits-1)) & mask;
  98   if (masked_msbs != 0 && masked_msbs != mask)
  99     return -1;
 100
 101   reg_t base = proc->get_state()->sptbr;
 102   int ptshift = (levels - 1) * ptidxbits;
 103   for (int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 104     reg_t idx = (addr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 105
 106     // check that physical address of PTE is legal
 107     reg_t pte_addr = base + idx * ptesize;
 108     if (pte_addr >= memsz)
 109       break;
 110
 111     void* ppte = mem + pte_addr;
 112     reg_t pte = ptesize == 4 ? *(uint32_t*)ppte : *(uint64_t*)ppte;
 113     reg_t ppn = pte >> PTE_PPN_SHIFT;
 114
 115     if (PTE_TABLE(pte)) { // next level of page table
 116       base = ppn << PGSHIFT;
 117     } else if (!PTE_CHECK_PERM(pte, supervisor, store, fetch)) {
 118       break;
 119     } else {
 120       // set referenced and possibly dirty bits.
 121       *(uint32_t*)ppte |= PTE_R | (store * PTE_D);
 122       // for superpage mappings, make a fake leaf PTE for the TLB's benefit.
 123       reg_t vpn = addr >> PGSHIFT;
 124       reg_t addr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
 125
 126       // check that physical address is legal
 127       if (addr >= memsz)
 128         break;
 129
 130       return addr;
 131     }
 132   }
 133
 134   return -1;
 135 }
 136
 137 void mmu_t::register_memtracer(memtracer_t* t)
 138 {
 139   flush_tlb();
 140   tracer.hook(t);
 141 }